DIGITAL-LOGIC AG
PCCP5 Manual V2.3
35
CMOS Map
Continued...
Location
Description
28h
Byte 3
bits 7-6 = Reserved
bits 5-0 = Upper 6 Bits of Write Precompensation
29h
Byte 4
bits 7-0 = Number of Heads
2Ah
Byte 5
bits 7-0 = Sectors Per Track
2Bh
Boot Password
bit 7
= Enable/Disable Password
0
=
Disable Password
1
=
Enable Password
bits 6-0 = Calculated Password
2Ch
SCU Password
bit 7
= Enable/Disable Password
0
=
Disable Password
1
=
Enable Password
bits 6-0 = Calculated Password
2Dh
Reserved
2Eh
High Byte of Checksum - Locations 10h to 2Dh
2Fh
Low Byte of Checksum - Locations 10h to 2Dh
30h
Extended RAM (KB) detected by POST - Low Byte
31h
Extended RAM (KB) detected by POST - High Byte
32h
BCD Value for Century
33h
Base Memory Installed
bit 7
= Flag for Memory Size
0
=
640KB
1
=
512KB
bits 6-0 = Reserved
34h
Minor CPU Revision
Differentiates CPUs within a CPU type (i.e., 486SX vs 486 DX,
vs 486 DX/2). This is crucial for correctly determining CPU
input clock frequency. During a power on reset, Reg DL holds
minor CPU revision.
35h
Major CPU Revision
Differentiates between different CPUs (i.e., 386, 486, Pentium).
This is crucial for correctly determining CPU input clock fre-
quency. During a power on reset, Reg DH holds major CPU
revision.
36h
Hotkey Usage
bits 7-6 = Reserved
bit 5
= Semaphore for Completed POST
bit 4
= Semaphore for 0 Volt POST
(not currently used)
bit 3
= Semaphore for already in SCU menu
bit 2
= Semaphore for already in PM menu
bit 1
= Semaphore for SCU menu call pending
bit 0
= Semaphore for PM menu call pending
40h-7Fh
Definitions for these locations vary depending on the chipset.
