SERVICE
35
MAGNET POWER SUPPLY SYSTEM 8500
Please refer to the plug description for a detail information on all possible inputs and outputs.
A delay-line ensures that an interlock signal only is accepted, if it stays high for longer than app. 100
mSec. R87, C42, R86 and C41. This in order to eliminate false noise generated interlocks. The
output of the delay-line will trigger Q10, Q11 that acts like a thyristor and thereby turns off the opto
coupler ISO21 that controls the main contactor. The sum interlock signal is also connected to the
LED D6 for a latched interlock.
Turning the power supply ON is initiated by turning Q7 on for a certain pulse with (programable but
½ a second as default). ISO21 will if allowable (no interlock) conduct turning the main contactor on.
This will in turn activate the PW_IS_ON line that will direct Q6 on, and thereby let the power supply
in the on state. If though for some reason the main contactor doesn’t goes on within the ON pulse
time of Q7 will the ON sequence be terminated.
If the
ì
P. wants to turn OFF the power supply (as a response to a command from the local control
panel or the remote line) it activates Q4 that forces Q7 and Q6 OFF.
For safety reasons the main interlock chain is as previously explained hard wired.The display of an
interlock event however is controlled by the FPGA and the CPU. The latched interlock information
can be seen from the LED’s (LD22-LD45), on the local control panel and it can be requested via the
remote line via an S1 command.
Each interlock is individually connected to FPGA. Every time an edge transition is detected it will
be latched in an internal register. The first one must though come with sum interlock.
On arriving of the first interlock, the FPGA will store this interlock together with status information
in a first catch register. The time of arrival will also be stored. These values can be red from the
remote serial line with the commands “S1FIRST” and “S1TIME”.
4.2.6.
DAC control:
The DAC control block produces the bits to the Digital to Analog Converter located in the regulation
module for setting the output current level. (see diagram sheet 4)
This function is realized inside the FPGA, but in the CAMAC operating mode the FPGA only
watches the bits for display purposes only.
The system can manage the DAC setting with up to 24 bit resolution (only 20 bit resolution is
actualized at the present stage). In serial control operation are the bits passed to the FPGA from the
ì
-Processor.
If a CAMAC- or a custom made- board (parallel) is plugged into P3 (P3 pin A32 pulled low) and the
system is in remote control, are the DAC bits passed from the IC24, IC26 and IC28 (see sheet 4) to
the DAC buffers IC18, IC19 and IC2.
The DAC control has also an influence on the SW ramp profile feature (Aviable as option). It
automatically smoothen out the “current set” step values given by the software by a hardware
interpolating counter between the two points.
DANFYSIK A/S - DK 2630 TAASTRUP - DENMARK.
DOC NO P80303Sk
