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SERVICE

36

MAGNET POWER SUPPLY SYSTEM 8500 

For further information on the Soft Ware controlled ramp profile features, please see the chapter “3.3 
Operating by RS232or RS422 I/O”

4.2.7.

Analog measurements:

Different  voltages  are  monitored  by  means  of  Analog  to  Digital  converters,  as  internal  supply
voltages and DAC-BOX delta temperatures and as well external values as output load currents and
voltages.
The following analog signals are monitored:

LOGICAL

PHYSICAL

BIT

CHANNEL CHANNEL

VALUE

RESOLUTION

0

IC34/CH0

Output current

11 + sign

1

IC34/CH3

Tesla (+1V)

11 + sign

2

IC34/CH2

Output Voltage

11 + sign

3

IC16/CH1

In15V sup.

10

4

IC16/CH2

IInternal -15V sup.

10

5

IC16/CH3

In5V sup.

10

6

IC34/CH1

Delta temperature

11 + sign

7

IC34/CH5

Trans. Bank Vce

11 + sign

8

Piggy Board/CH0

Optional Iout (16 Bit)

16 + sign

9

Mirror of logical channel 0

10

Mirror of logical channel 8

11

IC34/CH6

Iout Optional

11 + sign

12

IC34/CH4

Vout Optional

11 + sign

13

FPGA

Water flow

16

14

IC34/CH7

Free on plug P29 (±1V)

11 + sign

15

IC16/CH0

Free on plug P19 (10V)

10

The ADC block can be seen no sheet 3 of the schematic 83853. The 10 bit converters are located
inside the CPU IC16.

The measurements are available both on the local control panel and the serial remote lines. 

The reference voltage for the ADC converters comes from IC30 that delivers a voltage of 4.096V
which can be measured on TP23.

The burden resistor on the regulation board receives one Ampere for 100% output current. The
voltage of the burden resistor is measured by a high input impedance low drift differential amplifier
A1 to give an excellent measurement, especially when the optional 16 bit ADC is used.

Adjustment and calibration of the AD channels are mainly performed by changing the ADC scale
factor    through  SW  for  each  channel.  Only  the  VCE  reading  and  the  Iout  Off-set  value  can  be
trimmed  through  potentiometers.  Please  se  the  picture  on  the  next  page  for  a  more  detailed
visualization of the potentiometer locations and the different plugs including the user analog inputs.
The plug description later in this chapter input resolution for the different AD channels.

DANFYSIK A/S - DK 2630 TAASTRUP - DENMARK. 

DOC NO P80303Sk

Summary of Contents for 81083852

Page 1: ...ersion Part No 81083852 Prepared By Approved by Name P A Elki r Date 09 FebruarY 2009 Signature M A N U A L SMT CONTROL MODULE SYSTEM 8500 DANFYSIK A S DK 4040 Jyllinge Denmark Tel 45 46 79 00 00 Fax...

Page 2: ...t SW 1 7 PAE 08 Dec 2003 SW version SCS110 RS485 Always answer 48 Without SW 1 8 PAE 14 Aug 2008 SW version SCS113 ON OFF control Auto Slew Rate option 50 2 0 PAE 09 Feb 2009 SW version SCS114 Auto sl...

Page 3: ...3 3 4 Software Profile Programming 22 3 3 5 Two level value set 27 3 3 5 1 Using the two level function 28 3 3 6 SW Commands 29 4 Theory of operation 32 4 2 Control Board 32 4 2 1 Processor 32 4 2 2...

Page 4: ...arranty shall not apply to any equipment which have become defective or unworkable due to mishandling improper maintenance incorrect use radiation damage or any other circumstance not generally accept...

Page 5: ...componentsthat maybedamagebyelectrostaticdischarge or wrong handling Please handle with care and leave the modules inside the anti static bags as long as possible If the modules are damaged in any way...

Page 6: ...n S2 SETUP or through SW commands Please refer to the ESC commands in the SW appendix chapter for further information The two dip switches are configured as a multi func tion port that will be validat...

Page 7: ...t ups to the factory default can be accomplished as follows Short circuit ST60 just below SW2 Press at the same time S2 continuously All green parameter LEDs will start flashing After the fifth flash...

Page 8: ...lines can be set SW2 selects which line to set up Hint Selecting SW2 will immediately display the present setting on the green LEDs left to SW1 Parameters Default setting after COLD BOOT Local Line 96...

Page 9: ...ing problems has to be taken into consideration to avoid communication problems due to noise and high differential voltages that may jam the input signals The REMOTE line addressing can be used for co...

Page 10: ...et bit 1 OK Answer mode Disabled BOOT character FF R NU Disabled XON XOFF Protocol Disabled NU Disabled Local Line RS485 Communication Disabled 1 RS485 Line turn around time 0 Line turn around set bit...

Page 11: ...he below shown switch settings describe the possible Wake up conditions Parameters Default setting after COLD BOOT Remote addressing Disabled Local addressing Disabled Default line in Local Remote Aut...

Page 12: ...s WA 000123 For trailing zeroes WA 123 equals WA 123000 Parameters Default setting after COLD BOOT DAC 16 17 Transparent Interlock clear OFF CLEAR resets interlocks WA Zeroes WA command uses trailing...

Page 13: ...pplies requires a longer ON pulse for latching ON This due to the extended charging time when containing large capacitor banks Typical for switch mode supplies Parameters Default setting after COLD BO...

Page 14: ...The Auxiliary output line 1 can be programmed to produce a pulse or a static level output software command N1 F1 Below are the settings for this Auxiliary line Parameters Default setting after COLD B...

Page 15: ...e and to use the output port as an auxiliary output line a new software configuration must be given This can only be done by authorised Danfysik service personnel If enabled the Auxiliary 2 output lin...

Page 16: ...of the time delay can be set from 0 to 25 5 seconds this for letting the rest energy in the magnet to decay The time delay is only inserted if the power supply was ON before invoking the POL command T...

Page 17: ...rent read back readings This is useful when connected to a regulation loop that requires a positive signal feed back negative signal feed back is normal for System 8500 Lever 2 will inverse the status...

Page 18: ...ion To activate the automatic OFFSET adjustment following steps must be performed Select SW2 as above setting number14 Select the desired channel number lever 1 to 5 on SW1 Set lever 8 on SW1 to OFF T...

Page 19: ...value please use the Esc ADSET command To activate the automatic GAIN adjustment following steps must be performed Select SW2 as above setting number14 Select the desired channel number lever 1 to 5...

Page 20: ...fset value to default factory setting Zero please set lever 7 to one before pressing the Setup Button GAIN adjustment The GAIN adjustment can automatically adjust the scaling factor of the selected ch...

Page 21: ...st be left open Remote line RS232 Jumper on ST9 ST10 and ST11 must be left open RS422 Jumper on ST10 ST9 and ST11 must be left open RS485 Jumper on ST11 ST9 and ST10 must be left open RS485 Jumper on...

Page 22: ...power supply is able to execute up to 200 commands a second depending of the complexity of each command Ps Issuing short commands faster than the time to transmit the answer eg S1 will overload the in...

Page 23: ...ERROR_HANDLING REM Yes then go to error module ENDIF J 1 DO REM evaluate status reply IF MID S1 J 1 GOSUB STATUS J _ACTIVE REM set this status bit active ELSE GOSUB STATUS J _ACTIVE REM set this statu...

Page 24: ...version SCC108 Method C From software version SCC113 3 3 4 1 Arbitrary point ramp profile method With the Arbitrary point method it is possible to download up to fifteen independent points each genera...

Page 25: ...necting the master trig output P33 pin 3 4 to the other supplies trig input will start the other supplies when the master is triggered A maximum skew of 5 s between the supplies may be expected an ext...

Page 26: ...y auto loop RAMP RL or HW triggered auto armed RAMP TW For a full documentation on controlling the Equal time slot method please refer to the appendix 2 Ramp Profile Commands If synchronisation to an...

Page 27: ...has both its benefit and draw backs The cosines shape is smooth all the way but has a higher dI dt in the middle and results in a sinus output voltage shape on an inductive load whereas the square sh...

Page 28: ...be given in a floating point representation normalized to 1 000000 The time slot may be between 0 0125 to 1 second given in a floating point representation normalized to 1 0000 Maximum numbers of stac...

Page 29: ...enabled is partially implemented in HW inside the FPGA and SW If this function is not used set register 0 will be default selected making the system both HW and SW compatible with previous versions T...

Page 30: ...it 5 setup setting see SW command manual in appendix 1 on how to set the AUX2 bits If AUX2 bit 5 is zero SW control will the used register to the DAC follow the val2 information issued by the da 0 val...

Page 31: ...isten ALL LOC Change to Local Control LOCK Lock the MPS in Local Control N Main Power ON N1 Auxiliary 1 output line ON N2 Auxiliary 2 output line ON NASW No answer mode NERR No error message PO Polari...

Page 32: ...puts Esc LINE Configures the protocol for the serial lines Esc POLDELAY Plarity change over delay time in OFF Esc PPULS Configures the ON pulse width Esc PPULS1 Auxiliary line ON pulse width Following...

Page 33: ...e stack operation RR Read ramp status RAMPSET Time Multiplicant TrDly LWN C Configures the ramp operation SW RAMP PROFILE COMMANDS for Auto slew rate method summary Esc SLOPETIME Set slew rate time fo...

Page 34: ...terlock control DAC control Current setting and ramp profile interpolation ADC control Analog measurements Setting up the board parameters Ramp profile HW interpolation and synchronization Water Flow...

Page 35: ...lers ISO1 to ISO6 and a separate isolated voltage supply The lines are administered by the serial controllers inside the CPU controlling the baud rate parity check and the data format see page 5 The d...

Page 36: ...emote operation will the FPGA IC20 reroute the DAC setting bits to the regulation module Be aware if A32 is left open will the DAC setting buffer s be directed as outputs This enables parallel operati...

Page 37: ...rom the LED s LD22 LD45 on the local control panel and it can be requested via the remote line via an S1 command Each interlock is individually connected to FPGA Every time an edge transition is detec...

Page 38: ...P29 1V 11 sign 15 IC16 CH0 Free on plug P19 10V 10 The ADC block can be seen no sheet 3 of the schematic 83853 The 10 bit converters are located inside the CPU IC16 The measurements are available bot...

Page 39: ...SERVICE 37 MAGNET POWER SUPPLY SYSTEM 8500 DANFYSIK A S DK 2630 TAASTRUP DENMARK DOC NO P80303Sk...

Page 40: ...ter flow sensor giving pulses proportional to the flow rate can be attached to P21 The water flow sensor must have a TTL compatible output signal Totem Pole or open collector Pin 1 and 3 of P21 can be...

Page 41: ...refer to the ESC commands in the SW appendix chapter for further information The two dip switches are configured as a multi function port that will be validated by the CPU upon pressing the button S2...

Page 42: ...SERVICE 40 MAGNET POWER SUPPLY SYSTEM 8500 DANFYSIK A S DK 2630 TAASTRUP DENMARK DOC NO P80303Sk...

Page 43: ...lines power supply outputs P16 Four optional non galvanically isolated inputs P17 Local RS232 Service connector not mounted P18 Remote RS234 Service connector not mounted P19 Optional 10bit Analog inp...

Page 44: ...E SCHEMATIC ASSEMBLY Dwg No Dwg No Control Module SMT 83853B 83852A 16 Bit ADC SMT 83914 83913 10 Parts Lists MODULE PART NUMBER Control Board SMT 8100083852 13 16 Bit ADC SMT 8100083913 only if appli...

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