DS3112
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Bit
#
Register Name:
BERTRP0
Register Description:
BERT Repetitive Pattern 0 (lower word)
Register Address:
74h
7 6 5 4 3 2 1 0
Name RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
Default
0 0 0 0 0 0 0 0
Bit
# 15 14 13 12
RP12
11 10 9 8
Name RP15 RP14 RP13
RP11 RP10 RP9 RP8
Default
0 0 0 0 0 0 0 0
Register Name:
BERTRP1
Register Description:
BERT Repetitive Pattern 1 (upper word)
Register Address:
76h
Bit
# 7 6 5 4 3 2 1 0
Name RP23 RP22 RP21 RP20 RP19 RP18 RP17 RP16
Default
0 0 0 0 0 0 0 0
Bit
# 15 14 13 12 11 10 9 8
Name RP31 RP30 RP29 RP28 RP27 RP26 RP25 RP24
Default
0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31: BERT Repetitive Pattern Set (RP0 to RP31).
RP0 is the LSB and RP31 is the MSB. These registers
must be properly loaded for the BERT to properly generate and synchronize to either a repetitive pattern, a
pseudorandom pattern, or a alternating word pattern. For a repetitive pattern that is less than 17 bits, then the
pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the
repeating 5-bit pattern …01101… (where rightmost bit is one sent first and received first) then BERTRP0 should
be loaded with xB5AD and BERTRP1 should be loaded with x5AD6. For a pseudorandom pattern, both registers
should be loaded with all ones (i.e., xFFFF). For an alternating word pattern, one word should be placed into
BERTRP0 and the other word should be placed into BERTRP1. For example, if the DDS stress pattern “7E” is to
be described, the user would place x0000 in BERTRP0 and x7E7E in BERTRP1 and the alternating word counter
would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.