REGISTERS
3.7 Interrupt Queue Pointer Register 06
Contains the onboard RAM starting location of the Standard Priority Interrupt Queue
(initialized by host). This register is updated by the DTI-VME/S with the address of the next
entry in the queue when an interrupt block is written to the queue.
3.8 High Priority Interrupt Enable Register 07
MSB
LSB
15 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA
ERR
CMD
ERR
DYN
BUS
SS
FAIL
END
BIT
BIT
FAIL
EOL MSG
ERR
STD
INT
X X X X X X X 1 1 1 1 1 1 1 1 1
Reserved
Bits 15-9
Reserved
Bit 8
DMA ERR - Data Overrun Enable.
Data Overrun indicates that an internal DMA grant for access to the onboard RAM was not
received by the DTI-VME/S within the allocated time required for a successful data transfer to
memory.
Bits 7
CMD ERR - Illogical Command Error Enable (BC).
This bit enables a high priority interrupt to be asserted upon the occurrence of an Illogical
Command. Illogical commands include incorrectly formatted RT-to-RT Command Blocks.
Bit 6
DYN BUS - Dynamic Bus Control Mode Code Interrupt Enable.
Used in conjunction with the Dynamic Bus Control Bit in the RT Address Register to generate a
high priority interrupt.
Bit 5
SS FAIL - Subsystem Fail Enable.
Enables the high priority interrupt when receiving a SSYSF input.
Bit 4
END BIT - End of BIT Enable.
Indicates the end of the internal BIT routine.
Bit 3
BIT FAIL - BIT Word Fail Enable.
Enables the high priority interrupt upon the detection of a BIT failure.
Bit 2
EOL - End of Buslist (BC).
Enables the high priority interrupt when the end of the buslist is reached. This interrupt can be
superseded by other high priority interrupts.
Bit 1
MSG ERR - Message Error Enable.
Enables interrupts on bus message errors in the BC, RT or BM mode.
Bit 0
STD/INT - Standard Interrupt Enable.
Enables all standard interrupts to notify the host.
Copyright 2004
3-8
DTI-VME/S
Summary of Contents for DTI-VME/S
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