Curtiss-Wright DTI-VME/S, User Manual

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GETTING STARTED
high priority vector or the advantage of separate vector values is lost. The default address
for this register is 0x0081. Bits 0 through 15 are Standard priority interrupt vector bits.
2.6.7 Register 31: High Priority Interrupt Vector
This register holds the response to be placed on the data bus during an interrupt acknowledge
cycle for the high priority level selected with Bits 5 - 3 of Register 29. If Bit 6 of Register
29 is 0 (8-bit vector), the upper byte of response data is 0x00FF (all 1s). When READs are
made to Register 31 while the 8-bit vector is selected. the upper byte is always read as all 1s.
Different VME host processors have different interrupt schemes; therefore, select an
interrupt vector that does not conflict with a location already used by the host operating
system. The high priority vector should be set to a different value than the standard priority
vector or the advantage of separate vector values is lost. The default address for this register
is 0x0080. Bits 0 through 15 are High priority interrupt vector bits.
2.7 Step 7. Basic Commands For The BC, RT and BM
2.7.1 BC Operational Sequence with Interrupts
1. Set up the first Command Block instruction block for a four-word RT-to-BC transfer
(Control Word, Command Word 1) and initialize Register 2 with the onboard RAM
address of the beginning of the block.
2. Enable the auto-retry on the opposite bus using only one retry attempt, if the incoming
message is received with a message error. (Control Register 0 = 0x0C90; Bus A
enabled).
3. Set the End Of List Bit in the control word (0x2C00), Interrupt And Continue Bit, and
the Auto Retry Enable Bit.
4. Set up the data list pointer to store all data words in the preferred area of memory.
5. Configure the standard interrupt queue in the preferred area of memory and initialize
Register 5 with the onboard RAM address of the beginning of the queue.
6. Enable the Standard Interrupt Bit and the End Of List Bit in the High Priority Interrupt
Enable Register. Enable the Command Block Interrupt Bit in the Standard Interrupt
Enable Register.
7. Set the Start Enable Bit in the Control Register (Register 0).
8. Message implementation now begins by transmitting the transmit command stored in
the Command Block. The DTI-VME/S waits to receive the status word book from the
transmitting RT.
9. The status word is received and stored in Command Block 1. The incoming data
words from the transmitting RT follow and the DTI-VME/S stores them in memory as
pointed to by the data list pointer.
10. The DTI-VME/S, having encountered the End Of List Bit being set, halts message
transactions and waits for another start signal.
Copyright 2004 2-11 DTI-VME/S