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REGISTERS

3.18 Bus Monitor Terminal Address Select (RT 16 - 31) 17

If Bit 13 of Register 14 is set, setting the appropriate bit in this register enables monitoring
of the selected RT.

MSB

LSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R34

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3.19 Master Reset Register 18

A READ of Register 18 initializes a Master Reset on the DTI-VME/S, clearing all
sequencers and internal registers. Memory is not cleared. The READ data is not
meaningful.

MSB

LSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRX

BUS

A/B

TRX

BIT

X X X X X X X X X X X X 1/0

1/0

Reserved

(Must be 0)

The following definitions are valid for writes.

Bits 15-4

Reserved (Must be 0).

Bit 3

TRX EN - Transceiver Enabled.

Write : 0 = Enable Transceiver. 1 = Disable Transceiver.

Bit 2

BUS A/B - Bus A/B Enable.

Write: 0 = Bus B. 1 = Bus A.

Bit 1

TRX MC - Transmit Mode Code.

Write: 0 = Transmit Mode Code 3 to RT 30. 1 = Transmit Mode Code 19 to RT 30 on self-test.

Bit 0

ST BIT - Start BIT Test.

To start the BIT Test, WRITE a 0 and then a 1.

3-13

DTI-VME/S

Summary of Contents for DTI-VME/S

Page 1: ...DTI VME S User Manual Document No T T MU DTXXVS A 0 A2 ...

Page 2: ......

Page 3: ... no warranty of any kind with regard to this printed material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Copyright 2004 Systran Division of Curtiss Wright Controls Inc All Rights Reserved Revised September 3 2004 Previously DTI Doc No 88 30003 Curtiss Wright Controls Inc Embedded Computing Data Communications 2600 Paramount Place Sui...

Page 4: ...ion which may interfere with other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this product has no intrinsic function and is therefore not subject to European Union CE EMC directive 89 336 EEC ...

Page 5: ... 6 4 Register 28 Extended Address Select 2 8 2 6 5 Register 29 Interrupt Level and Vector Width Selection 2 9 2 6 6 Register 30 Standard Priority Interrupt Vector 2 10 2 6 7 Register 31 High Priority Interrupt Vector 2 10 2 7 Step 7 Basic Commands For The BC RT and BM 2 11 2 7 1 BC Operational Sequence with Interrupts 2 11 2 7 2 RT Operational Sequence with Interrupts 2 11 2 7 3 BM Operational Seq...

Page 6: ...rrupt Enable Register 09 4 5 4 5 5 Interrupt Counter Read Clear Register 19 4 6 4 5 6 Autodecrement Interrupt Counter Register 20 4 6 5 BUS CONTROLLER MODE OF OPERATION 5 1 5 1 Bus Controller Structure 5 2 5 1 1 Head Pointer 5 2 5 1 2 Control Word 5 2 5 1 3 Command Word One 5 4 5 1 4 Command Word Two 5 4 5 1 5 Data Pointer 5 4 5 1 6 Status Word Two 5 4 5 1 7 Status Word Two 5 4 5 1 8 Tail Pointer ...

Page 7: ... Bus Monitor Control Register 14 7 3 7 3 2 Bus Monitor Terminal Address Select Registers 16 and 17 7 3 7 3 3 Interrupt Queue Pointer Register 06 7 4 7 3 4 Next Message Record Block Register 02 7 4 7 3 5 Control Register 00 7 4 7 3 6 High Priority Interrupt Register 07 and Standard Interrupt Register 09 7 4 7 3 7 Reset Timer Register 13 7 4 7 3 8 Remote Terminal Address Register 10 7 4 7 4 Collecti...

Page 9: ...C to RT RT to BC and RT to RT instructions mode code broadcast mode and broadcast For applications requiring a high degree of host processing the following functions may be incorporated without host intervention Interrupt Lists Multiple Message Processing Automatic Polling Variable Memory Space Allocation Selectable Data Storage Indexing This architecture is also effective when multiple DTI VME Ss...

Page 10: ... the 64K word dual port RAM the DTI VME S receives stores time tags and counts over 2 000 32 data word transfers Bus messages are transmitted and received without host intervention As each valid bus message is received an RT index counts the number if storage buffers If the buffers for a particular subaddress are full only the last message buffer is overwritten Other RT features include Generating...

Page 11: ...this manual Standard priority interrupts are queued and handled via application requirements The host can periodically or continuously monitor the number of standard priority interrupts queued The standard priority interrupt queue is initialized by the host and consists of a first in first out queue of enabled interrupt events The standard priority interrupt queue holds up to 255 packets or entrie...

Page 12: ... RAM Word size 16 bits Communication MIL STD 1553B protocol dual redundant bus Interface to bus Transformer or direct coupling Voltage 5 0V 5 12 0V 5 12 0V 5 Current Drain 2 3 amperes maximum single channel 3 3 amperes maximum dual channel Temperature range Operating Storage 0 to 70 degrees Celsius 55 to 125 degrees Celsius Relative humidity 10 to 90 non condensing Processor clock speed 12 megaher...

Page 13: ...assessed Curtiss Wright Controls Quality System BSI s Quality Assurance division certified we meet or exceed all applicable international standards and issued Certificate of Registration number FM 31468 on May 16 1995 The scope of Curtiss Wright Controls registration is Design manufacture and service of high technology hardware and software computer communications products The registration is main...

Page 14: ... systran com Fax 937 252 1465 World Wide Web address www systran com 1 13 Ordering Process To learn more about Curtiss Wright Controls products or to place an order please use the following contact information Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phone 937 252 5601 or 800 252 5601 E mail info systran com World Wide Web address www systran com Copyright 20...

Page 15: ... not remove the board from the protective bag until grounded Once grounded remove the board from the protective bag and place the board on the bag or any electrostatically controlled surface RSW3 RSW2 RSW1 SYSTRAN Corporation JP2 Figure 2 1 DTI VME S Board Examine the board If the board appears to be damaged contact Curtiss Wright Controls immediately Copyright 2004 2 1 DTI VME S ...

Page 16: ...2 RSW2 0 A 6 RSW1 RSW2 RSW3 6 A 0 Caution Install the DTI VME S with power off 1 Locate an available slot in the host computer 2 Jumper the daisy chained signal IACKIN IACKOUT on all unu board is inserted in Slot 2 shown in Figure 2 3 the IACK ju Empty Slot Slot 1 Slot 2 Slot 3 DTI VME Empty Slot IACK Jumper Installed IACK Jumper Installed Inserted in Slot 2 the CPU and the DTI VME S enabling the ...

Page 17: ...an RT for interaction betw DTI VME S CHANNEL 1 EXT 1 CHANNEL 2 EXT 2 Pin 1 Output Pin 2 Input Pin 4 Ground Pin 3 Input Pin 1 Output Pin 2 Input Pin 4 Ground Pin 3 Input P6 P5B A B A B INV IMP BUS ERR SYSTRAN Corporation 51 52 53 Figure 2 4 The DTI VME S External Ports he TTL level signals for the external port follow 2 4 1 Pin 1 Command Strobe Output ving a valid 1553B command and deactivates the ...

Page 18: ... registers replace hardware programmable switches and jumpers The I O base address is the only hardware programmable option the user must select See Step 2 The bits in the programmable registers are set to their default values when the system is powered up or a system hardware reset is performed The software reset performed by reading Register 18 does not affect the register settings Existing conf...

Page 19: ... 1 is written to Bit 0 position of Register 18 a built in test state machine pattern generator sends a 1553 bus encoded message The selection of one of two messages whether Bus A or B is used and transmitter enabling is also done using bits in Register 18 If this bit is set to 0 the test pattern is generated once for each write to Register 18 If this bit is set to 1 one write to Register 18 enable...

Page 20: ... six bits of this register are used to select the dual port RAM size offset the start address of the selected amount of dual port RAM and select the bank of onboard RAM to be used for dual port operation The DTI VME S can address 64K words of memory therefore this is the maximum size of space that can be allotted in the VME memory address space However the user has the option of selecting smaller ...

Page 21: ... the 128 KB segment of RAM being shared by the DTI VME S and the VME host By switching memory banks various bus contexts can be changed rapidly by the host The DTI VME S must be in an idle state during any bank switching operation 00 Bank 0 lower 64 K words 01 Bank 1 next 64 K words 10 Bank 2 next 64 K words 11 Bank 3 upper 64 K words 00 Default Bits 3 2 RAM Address Offset These two bits can offse...

Page 22: ...en time The board does not occupy both spaces simultaneously Avoid overlapping the DTI VME S address space with another device in the A32 and A24 system address space For a standard 24 bit memory address use Register 27 to set the base starting address For an extended 32 bit memory address use Registers 27 and 28 to set the base starting address of dual port RAM Example If setting an extended 32 b...

Page 23: ...its in Register 27 to initiate a memory cycle MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A31 A30 A29 A28 A27 A26 A25 A24 Reserved X X X X X X X X 1 1 1 1 1 1 1 1 NOTE Bits 8 through 15 are reserved 0 Base address signal A24 1 A25 2 A26 3 A27 4 A28 5 A29 6 A30 7 A31 2 6 5 Register 29 Interrupt Level and Vector Width Selection Seven bits in this register are used to perform the following select t...

Page 24: ...ty level than standard priority interrupts The front panel INV LED will light if the standard priority interrupt level is greater than the high priority interrupt level Bits 2 0 Standard Priority Interrupt Level These three bits are used to select the standard priority interrupt level 000 Illegal 001 Level 1 lowest 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 111 Level 7 highest non...

Page 25: ...fer Control Word Command Word 1 and initialize Register 2 with the onboard RAM address of the beginning of the block 2 Enable the auto retry on the opposite bus using only one retry attempt if the incoming message is received with a message error Control Register 0 0x0C90 Bus A enabled 3 Set the End Of List Bit in the control word 0x2C00 Interrupt And Continue Bit and the Auto Retry Enable Bit 4 S...

Page 26: ...igure the standard interrupt queue in the preferred area of memory and initialize Register 06 with the onboard RAM address of the beginning of the queue 5 Select the desired RT in Register 10 6 Enable the Standard Interrupt Bit in the high priority interrupt enable register and the interrupt when index 0 bit in the control word 7 Enable the desired bus and set the Start Enable Bit in Register 00 8...

Page 27: ...ck Access Bit in the control status word of the monitor control block 6 Select the enable bit in the Bus Monitor Control Register Register 14 Select the RTs to monitor via Registers 14 16 and 17 7 Configure the standard interrupt queue in the preferred area of memory and initialize Register 06 with the onboard RAM address of the beginning of the queue 8 Set Bit 0 in Register 00 9 Message monitorin...

Page 29: ...dth These registers are Bus Connection Relay Control Register 25 Memory Size Start Address Bank Select Register 26 Standard Address Select Register 27 Extended Address Select Register 28 Interrupt Level and Vector Width Selection Register 29 Standard Priority Interrupt Vector Register 30 High Priority Interrupt Vector Register 31 See Getting Started for more information on the Configuration Regist...

Page 30: ...eset Timer Register 13 Bus Monitor Control Register 14 Bus Monitor Terminal Address Select Register 16 Bus Monitor Terminal Address Select Register 17 NOTE 1 Set Enable 0 Clear Disable Copyright 2004 3 2 DTI VME S ...

Page 31: ...enable external override used in a multi redundant system You need to ground the External Port Pin 3 Bit 10 RT BM BC RT BM or BC Select Select operating mode of DTI VME S BC 1 RT BM 0 Bit 9 RTY OPPB Retry on Opposite Bus BC Mode enables Retry on alternate bus If you have enabled Bus A for multiple retries via Bits 5 and 6 these retries take place on Bus B Bit 8 BUS B EN Enable Bus B RT BM Mode 1 e...

Page 32: ...age error bit is set in the 1553 RT status message Bit 1 RTY BSY Retry on Busy Bit BC Mode enables automatic RETRY on a received busy bit in the 1553 RT status response Bit 0 ST EN Start Enable Start Enable not READable for RT BM modes BC Mode starts restarts a buslist execution After any RESET the RT BM or buslist execution must be restarted via this bit Copyright 2004 3 4 DTI VME S ...

Page 33: ...tus Word Bit 11 SRQ Service Request Service Request Bit is set in the RT Status Word Bit 10 BUSY Busy Bit Busy Bit is set in the RT Status Word Bit 9 BIT Built In Test Built in Test in progress Bit 8 RST RESET RESET in progress Bit 7 BC RT BM Bus Controller Remote Terminal or Bus Monitor Mode Indicates the current mode of operation 1 BC 0 RT BM Bit 6 BUS A B Indicates the Bus in use or last used 1...

Page 34: ... mode this register contains the onboard RAM address for the next Message Record Block to be recorded 3 4 Polling Compare Register 03 MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Reserved Polling Compare Bits In the Polling Mode the RT Response is compared to the Polling Compare Register If any bits of the Polling Register match the Status Wor...

Page 35: ...ead out modified and re written to this register The contents of this register are transmitted onto the 1553 bus in response to a Mode Code 19 command Transmit BIT word 3 6 Current Command Register 05 Read Only In RT mode this register contains the command currently being processed When not processing a command the DTI VME S stores the last command or status transmitted on the 1553 bus This regist...

Page 36: ...h priority interrupt to be asserted upon the occurrence of an Illogical Command Illogical commands include incorrectly formatted RT to RT Command Blocks Bit 6 DYN BUS Dynamic Bus Control Mode Code Interrupt Enable Used in conjunction with the Dynamic Bus Control Bit in the RT Address Register to generate a high priority interrupt Bit 5 SS FAIL Subsystem Fail Enable Enables the high priority interr...

Page 37: ...al Broadcast Command Asserted upon the occurrence of an Illogical Command Illogical commands include incorrectly formatted RT to RT Command Blocks Bit 6 DYN BUS Dynamic Bus Control Acceptance Indicates that a Dynamic Bus Control command was received Bit 5 SS FAIL Subsystem Fail Indicates that a SSYSF input was received Bit 4 END BIT End of BIT Indicates the end of the internal BIT routine Bit 3 BI...

Page 38: ...s an interrupt indicating that all the programmed number of retries have failed Bit 1 MSG ERR Message Error Event BC RT BM This bit enables a standard interrupt for message errors Bit 0 CMD BLK Command Monitor Block Interrupt and Continue BC BM This bit enables an interrupt indicating that a Command Block Instruction or a Monitor Message block with the Interrupt and Continue function enabled has b...

Page 39: ... is set This is not a useful bit as it does not reflect the state of the BC RT Mode Select Bit Register 00 Bit 10 Bit 7 LOCK Change Lock Out Change Lock Out Enable When set this bit prohibits changes to the RT Address or the BC RT mode select using internal registers Bit 6 PAR ERR RT Address Parity Error This bit indicates an RT Address Parity Error It appears after the RT Address is latched if a ...

Page 40: ... Monitor All Terminals If set all RT activity is monitored If not set Bit 13 must be set Bit 13 MON RD TRM Monitor Register Declared Terminals If set RTs selected in Registers 16 ad 17 are monitored If not set Bit 14 must be set Bits 12 0 Reserved 3 16 Register 15 Reserved 3 17 Bus Monitor Terminal Address Select RT 0 15 16 If Bit 13 of Register 14 is set setting the appropriate bits in this regis...

Page 41: ...ng all sequencers and internal registers Memory is not cleared The READ data is not meaningful MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRX EN BUS A B TRX MC ST BIT X X X X X X X X X X X X 1 0 1 0 1 0 1 0 Reserved Must be 0 The following definitions are valid for writes Bits 15 4 Reserved Must be 0 Bit 3 TRX EN Transceiver Enabled Write 0 Enable Transceiver 1 Disable Transceiver Bit 2 BUS A B...

Page 42: ...s 256th This bit is cleared via a WRITE to Register 19 a master reset or a host system reset Bits 7 0 Interrupt Counter These bits store the number of interrupts held within the Standard Interrupt Queue A READ from this register returns the contents A WRITE clears the Exceed Bit and the Interrupt Counter Bits 3 21 Autodecrement Interrupt Counter Register 20 MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 43: ... that is controlled by writing to Register 18 Write 0 Single test pattern Write 1 Continuous looping test pattern Default 0 This bit is only useful for diagnostic test operation Bit 2 T D CPL Transformer Direct Coupling This bit can connect the 1553 bus transformer secondary windings to the bus in either the transformer coupled or direct coupled configuration Write 0 Transformer coupling selected ...

Page 44: ...t of RAM to be shared by the VME host and DTI VME S Write 00 Bank 0 lower 64 K Words Write 01 Bank 1 next 64 K Words Write 10 Bank 2 next 64 K Words Write 11 Bank 3 upper 64 K Words Default 0 NOTE The DTI VME S must be in an idle state during any bank switching operation Bits 3 2 RAM Address Offset These two bits can offset the address of the selected amount of dual port RAM The address is offset ...

Page 45: ...th the DTI VME S 3 25 Standard Address Select 27 This register represents the base address for standard A24 address space MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 Res X X X X X X X X 1 1 1 1 1 1 1 X Reserved 3 26 Extended Address Select 28 This register represents the base address for extended A32 address space MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A31 A30 ...

Page 46: ...0 Bits 5 3 High Priority Interrupt Level These three bits select the high priority interrupt level Write 000 Illegal Write 001 Level 1 lowest Write 010 Level 2 Write 011 Level 3 Write 100 Level 4 Write 101 Level 5 Write 110 Level 6 Write 111 Level 7 highest non maskable Default 2 Bits 2 0 Standard Priority Interrupt Level These three bits select the standard priority interrupt level Write 000 Ille...

Page 47: ... 8 bit vector is selected in Register 29 Bit 6 0 Bits 15 8 of this register always read as 1s 3 29 High Priority Interrupt Vector 31 The bits in this register contain the response placed on the data bus during an interrupt acknowledge cycle for the high priority level selected with Bits 5 3 of Register 29 If Bit 6 of Register 29 is 0 8 bit vector the upper byte of response data is 0x00FF The defau...

Page 49: ...ndard priority events enabled via bit 0 of the HP enable register YES YES YES NO NO NO Hp status register is enabled via a particular bit for the particular event Host is notified Is the event a bus message error Host handles the event as application Host halts system until event is serviced Figure 4 1 The Interrupt Process Once interrupted you have the option of reading the interrupt from a queue...

Page 50: ...upt level To set the high priority interrupt to Level 6 Bits 4 and 5 must each be set to 1 and Bit 3 must be set to 0 The high priority interrupt default is Level 2 High priority interrupts must be assigned a higher or equal priority level than standard priority interrupts The INV LED on the DTI VME S front panel lights to indicate the high priority interrupt level is lower than the standard prior...

Page 51: ...k Bit 14 No Response Time Out Bit 15 Set After a Write to Interrupt Status Word by DTI VME BC Location of Corresponding 16 Bit Onboard Buslist Instruction RT Location of Subaddress Mode Code Response Block or Monitor Message Record Block Interrupt Status Buslist Pointer Subaddress Mode Code Response Block Pointer Monitor Message Record Pointer Tail Pointer Interrupt Status Buslist Pointer Subaddre...

Page 52: ... to the queue the contents of this register are updated with the address of the next entry in the queue 4 5 2 High Priority Interrupt Enable Register 07 The High Priority Interrupt Enable Register allows you to select up to nine events to be enabled for high priority system handling When you enable an event as high priority the host is notified each time the event occurs To enable a particular eve...

Page 53: ...nerating a high priority interrupt until the corresponding status bit is reset by writing a 1 to that bit See page 3 9 for a bit explanation of this register MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAT OVR ILL CMD DYN BUS SS FAIL END BIT BIT FAIL EOL MSG ERR STD INT X X X X X X X 1 1 1 1 1 1 1 1 1 Reserved 4 5 4 Standard Priority Interrupt Enable Register 09 The Standard Priority Interrupt E...

Page 54: ...S ERR EXC 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Board Revision Level Interrupt Counter 4 5 6 Autodecrement Interrupt Counter Register 20 Each time a queued standard interrupt is serviced the interrupt queue counter must be reduced or decremented The Autodecrement Interrupt Counter Register provides the capability of reducing the queue counter By issuing a command READ or WRIT...

Page 55: ... bus instruction up to a maximum of 64 microseconds programmable at 16 usec resolution after the beginning of the current message Detecting protocol and bus errors including command and associated status word address comparisons response time out long and short word count bit count parity and Manchester II errors Initiating any broadcast or broadcast mode commands using RT Address 31 Polling RTs f...

Page 56: ... Request Instrumentation Bit Message Error Remote Terminal Address Head Pointer Control Word Command Word 1 Command Word 2 RT RT Only Data Pointer Status Word 1 Status Word 2 RT RT Only Tail Pointer Head Pointer Control Word Command Word 1 Command Word 2 RT RT Only Data Pointer Status Word 1 Status Word 2 RT RT Only Tail Pointer Figure 5 1 BC Command Block Structure 5 1 1 Head Pointer The 16 bit H...

Page 57: ...to RT transfer Bit 8 Monitor RT to RT Transfer Specifies RT to RT monitoring for the message enabled Because the data is stored in the BC s data buffer you can read data received transmitted between the two RTs Bits 7 0 Intermessage Timing These bits define the period of time from the start of the currently executing Command Block instruction to the start of the next sequential Command Block busli...

Page 58: ...ction is 32 or less 5 1 6 Status Word Two Status Word One is loaded when one of the following situations occurs RT Response Status for a BC to RT transfer or an RT to BC transfer Status Word of MIL STD 1553B mode code transfer RT Transmit Status for RT to RT transfer 5 1 7 Status Word Two The 16 bit Status Word Two contains the Receiving Status in RT to RT transfers If RT to RT transfers do not oc...

Page 59: ...status word followed by one data word The status word and data word transmit in one continuous fashion 5 2 2 Mode Command Without Data Word Transmit The DTI VME S issues a transmit command to the RT using a mode code specified in MIL STD 1553B After command word validation the RT transmits a status word 5 2 3 Mode Command With Data Word Receive The DTI VME S issues a receive command to the RT usin...

Page 60: ...broadcast option set the Broadcast Received Bit in the status word and do not transmit the status word 5 2 7 RT to RT Transfer Broadcast The DTI VME S issue a receive Command Word One with RT 31 11111 in the RT address field followed by a transmit command to another RT RT X using the selected broadcast of RT X After command word validation RT X transmits a status word followed by the specified num...

Page 61: ...pecific subaddress is addressed Storing data per subaddress in a first in first out FIFO methodology with time tag 6 1 RT Subaddress Response Block Structure The RT data structure includes a subaddress response block that is linked to any associated data words Figure 6 1 Each RT subaddress block includes the following four header words Control Word Message Status Pointer Data List Pointer Reserved...

Page 62: ... data is stored or transferred Via this bit you can determine if the bus message was sent to the correct RT subaddress or if the RT subaddress is supposed to be valid indicating that the RT configuration may be incorrect Bit 8 Interrupt Upon Valid Command Received If this bit is enabled a Subaddress Event Interrupt standard priority interrupt occurs when this subaddress is addressed Enabling this ...

Page 63: ...address Bit 13 Message Error This bit is set when any of the following errors occur Word Count Bit Count Manchester II including zero crossing deviation and rise and fall times parity data contiguity illegal subaddress or illegal broadcast subaddress Bits 12 8 Word Count Indicates the number of words stored from the transacted message Bits 7 0 Time Tag Indicates when the message was recorded in 64...

Page 64: ...eive Receive Receive Receive Unused Transmit Transmit Transmit Transmit Unused Subaddress 30 Subaddress 31 Subaddress 1 Subaddress 2 Subaddress 1 Subaddress 2 Subaddress 30 Subaddress 31 Mode Code Numbers 0 16 Mode Code Numbers 1 17 Mode Code Numbers 15 31 Figure 6 2 RT Subaddress and Mode Code Response Blocks 6 2 RT Subaddress Response Block Operation When the BC requests a transmit the RT s suba...

Page 65: ...itored To maximize data integrity only the last message of the queue is overwritten when the buffer fills up Interrupts may be generated when the buffer fills up 6 3 RT Mode Code Response Block Frequently the instruction sent to an RT takes the form of a mode code Table 6 1 displays the MIL STD 1553B mode codes supported by the DTI VME S Associated Mode Code Function Data Word Broadcast 0 Dynamic ...

Page 66: ...without data 16 31 refer to mode codes with data Bit 15 Interrupt on Reception of Mode Code without Data Word If this bit is enabled the RT interrupts when this mode code is transacted If this bit is set and the RT transacts this mode code without data a Specific Mode Code Interrupt occurs Bit 14 Illegalize Broadcast Mode Code without Data Word If this bit is enabled the RT does not accept this Br...

Page 67: ... standard priority interrupt occurs when the RT transacts this mode code with data and also sets the Message Error Bit in the message status word Mode codes may also be validated using this bit Bit 8 Interrupt When Mode Code with Data Word is Transacted This bit allows an interrupt to be generated when this mode code with data is transacted When the RT transacts this mode code with data a Subaddre...

Page 68: ...ontains a 16 bit address of the next available location for storing incoming data If the index field Bits 6 through 0 of the mode code block control word equals 0 the data list pointer is not incremented The last stored data is overwritten If the index field of the RT response messages control word does not equal 0 the data list pointer is updated with the next available data location at the end o...

Page 69: ...1553B Status Word and the Status Register Host intervention is required for the DTI VME S to take over as BC Bit 11 RT FLAG Terminal Flag RT Sets the 1553B Status Word Terminal Flag Bit The bit in the 1553B Status Word is also internally set if the BIT fails Bit 10 SRQ Service Request RT Sets the Status Word Service Request Bit Bit 9 BUSY1 Busy Mode Enable RT This bit sets the Status Word Busy Bit...

Page 70: ...RT Address Parity This is an odd parity used with the RT Address It ensures accurate recognition of the RT Bits 4 0 RT Address Modify the RT Address by writing to these bits Must be written after reset Copyright 2004 6 10 DTI VME S ...

Page 71: ...Message Record Blocks are linked through the tail pointer so that either the entire list or a portion of the list of Message Record Blocks can be rewritten Time Tag Bus A B Interrupt on Access 1553 Message Error Block Activated Data Word Count Mode Code Subaddress Mode Transmit Receive Remote Terminal Address Data Word Count Mode Code Subaddress Mode Transmit Receive Remote Terminal Address Data W...

Page 72: ... received or generate an interrupt every n messages n is a multiple of the total number of message record blocks If you set an interrupt after five messages you receive an interrupt at the end of the 10th 15th 20th interrupt Bit 12 Bus Indicator This bit specifies on which bus the message was received 1 Bus A 0 Bus B Bits 11 8 Reserved Bits 7 0 Time Tag These bits indicate the time in 64 microseco...

Page 73: ... Data Buffers If memory is cleared all data buffers contain 0s 7 3 Loading Bus Monitor Registers The Bus Monitor Control Register 14 and the Bus Monitor Terminal Address Select Registers 16 and 17 control the bus monitor The loading of these and other registers that affect the BM is described in the following sections 7 3 1 Bus Monitor Control Register 14 Bit 15 of this register enables the BM Bit...

Page 74: ...ust be cleared to 0 prior to starting the bus monitor 7 4 Collecting Data To ensure data stored in memory is not overwritten write data to disk and generate interrupts during message intervals For example you have 2 000 Message Record Blocks with an interrupt generated every 500 blocks The Interrupt Bit for Blocks 500 1 000 1 500 and 2 000 is set If upon interrupt a message is stored in any of the...

Page 75: ...BUS MONITOR Bit 14 of the control word is set and a message error has occurred Bit 12 of the control word is set and the message has been transmitted on Bus A Copyright 2004 7 5 DTI VME S ...

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Page 78: ......

Page 79: ...4 6 8 Data Pointer 5 4 7 3 Direct Coupling 2 5 3 15 dual channel board 2 5 Dual Port RAM 1 2 E Error 2 7 3 3 3 4 3 8 3 9 3 10 3 11 3 14 3 16 4 3 5 2 6 2 6 3 6 6 6 7 6 8 6 9 7 2 errors 7 1 Extended Address Select Register 3 1 External Ports 2 3 H High Priority Interrupt Enable Register 2 11 2 13 3 1 3 8 4 4 7 4 high priority interrupt level 2 10 High Priority Interrupt Level 2 10 3 18 4 2 High Prio...

Page 80: ...Reset Timer Register 3 2 3 12 7 4 Rotary Switches RS1 RS2 and RS3 2 2 RT Address Register 2 12 3 1 3 8 6 8 6 9 RT features 6 1 RT mode 6 1 RT Mode Code Subaddress Response Block 6 6 RT Operational Sequence with Interrupts 2 12 RT Registers 6 8 RT Subaddress and Mode Code Response Blocks 6 4 RT Subaddress Response Block 6 1 6 4 RT Subaddress Response Block Operation 6 4 RT Subaddress Response Block...

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