Since the triggers are only connected by OR in the triggerblock logic (see fig.
) they are
assigned to one of the gates each and connected with AND via the gating block region of the
trigger matrix (see fig.
and
). Because of the dead times of the gates it is important
to enable the retriggering feature. Furthermore a precursor of 2 clock cycles is needed, because
the gates are delayed in relation to the ADC samples.
upper threshold
lower threshold
upper level trigger
lower level trigger
upper AND lower
Figure 2.22: Measuring data with amplitude between an upper and a lower threshold by means
of two level triggers.
Config settings can be found in the following code snippet.
1
c o n f i g
.
t r i g g e r b l o c k
[ 0 ] .
e n a b l e d
= 1 ;
2
c o n f i g
.
t r i g g e r b l o c k
[ 0 ] .
p r e c u r s o r
= 2 ;
3
c o n f i g
.
t r i g g e r b l o c k
[ 0 ] .
l e n g t h
= 0 ;
4
c o n f i g
.
t r i g g e r b l o c k
[ 0 ] .
s o u r c e s
=
NDIGO TRIGGER SOURCE ONE
;
5
c o n f i g
.
t r i g g e r b l o c k
[ 0 ] .
g a t e s
=
NDIGO TRIGGER GATE 0
| ←
-
NDIGO TRIGGER GATE 1
;
6
c o n f i g
.
g a t i n g b l o c k
[ 0 ] .
r e t r i g g e r
= 1 ;
7
c o n f i g
.
g a t i n g b l o c k
[ 0 ] .
s t o p
= 0 ;
8
c o n f i g
.
g a t i n g b l o c k
[ 0 ] .
s o u r c e s
=
NDIGO TRIGGER A0
;
9
c o n f i g
.
g a t i n g b l o c k
[ 1 ] .
r e t r i g g e r
= 1 ;
10
c o n f i g
.
g a t i n g b l o c k
[ 1 ] .
s t o p
= 0 ;
11
c o n f i g
.
g a t i n g b l o c k
[ 1 ] .
s o u r c e s
=
NDIGO TRIGGER A1
;
12
c o n f i g
.
t r i g g e r
[
NDIGO TRIGGER A0
] .
r i s i n g
= 0 ;
13
c o n f i g
.
t r i g g e r
[
NDIGO TRIGGER A0
] .
t h r e s h o l d
= 1 0 0 0 0 ;
14
c o n f i g
.
t r i g g e r
[
NDIGO TRIGGER A1
] .
r i s i n g
= 1 ;
15
c o n f i g
.
t r i g g e r
[
NDIGO TRIGGER A1
] .
t h r e s h o l d
=
−
10000;
cronologic GmbH & Co. KG
17
Ndigo5G User Guide
Summary of Contents for Ndigo5G-10
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