Cronologic Ndigo5G-10, User Manual

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space only in case the FIFO is full. Therefore, if this number is 1.0 or more at least every second
packet in the DMA buffer is guaranteed to have the full length set by the gatelength parameters.
In many cases smaller values will also result in full length packets. But below a certain value
multiple packets that are cut off at the end will show up.
3.4.4 Structure ndigo gating block
ndigo bool t negate
Invert output polarity. Defaults to false.
ndigo bool t retrigger
Defaults to false. If retriggering is enabled the timer is reset to the value of the start parameter
whenever the input signal is set while waiting to reach the stop time.
ndigo bool t extend
Defaults to true. If set, a gate is created with the set timing from the first occurrence of the
input trigger even for short gates. If not set, the input signal must persist for the gate to be
created. This feature is NOT YET IMPLEMENTED.
ndigo bool t reserved1
Defaults to false. Do not change.
int start
In multiples of 3.2ns. The time from the first input signal seen in the idle state until the gating
output is set. The value of start needs to be less or equal to the stop value. Maximum value for
start and stop is 2
16
−
1.
int stop
In multiples of 3.2ns. Maximum allowed value is 2
16
−
1.
The time from leaving the idle state until the gating output is reset. If retriggering is enabled
the timer is reset to the value of the start parameter whenever the input signal is set while
waiting to reach the stop time.
int sources
A bit mask with a bit set for all trigger sources that can trigger this channel. The gates cannot
use the additional digital trigger sources
NDIGO TRIGGER SOURCE TDC PE to
NDIGO TRIGGER SOURCE BUS3 PE .
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