Cirrus Logic CS5460A, Manual

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CS5460A
28 DS284PP4
4.2 Pulse Output for Normal Format,
Stepper Motor Format and Mechanical
Counter Format
The duration and shape of the pulse outputs at the
EOUT and EDIR pins can be set for three different
output formats. The default setting is for Normal
output pulse format. When the pulse is set to either
of the other two formats, the time duration and/or
the relative timing of the EOUT and EDIR pulses is
increased/varied such that the pulses can drive ei-
ther an electro-mechanical counter or a stepper mo-
tor. The EOUT and EDIR output pins are capable
of
driving certain low-voltage/low-power
counters/stepper motors directly. This depends on
the drive current and voltage level requirements of
the counter/motor. The ability to set the pulse out-
put format to one of the three available formats is
controlled by setting certain bits in the Control
Register.
4.2.1 Normal Format
Referring to the description of the Control Register
in Section 5., REGISTER DESCRIPTION, if both
the MECH and STEP bits are set to ‘0’, the pulse
output format at the EOUT and EDIR pins is illus-
trated in Figure 10. These are active-low pulses
with very short duration. The pulse duration is an
integer multiple of MCLK cycles, approximately
equal to 1/16 of the period of the contents of the
Pulse-Rate Register. However for Pulse-Rate Reg-
ister settings less than the sampling rate (which is
[MCLK/8]/1024), the pulse duration will remain at
a constant duration, which is equal to the duration
of the pulses when the Pulse-Rate Register is set to
[MCLK/K]/1024. The maximum pulse frequency
from the EOUT pin is therefore [MCLK/K]/16.
When energy is positive, EDIR is always high.
When energy is negative, EDIR has the same out-
put as EOUT.
When MCLK/K is not equal to
4.096 MHz, the user can predict the pulse-rate by
first calculating what the pulse-rate would be if a
4.096MHz crystal is used (with K=1) and then scal-
ing the result by a factor of (MCLK/K) /
4.096MHz.
When set to run in Normal pulse output format, the
pulses may be sent out in “bursts” depending on
both the value of the Pulse-Rate Register as well as
the amount of billable energy that was registered by
the CS5460 over the most recent A/D sampling pe-
riod, which is (in Hz): 1 / [(MCLK/K) / 1024]. A
running total of the energy accumulation is main-
tained in an internal register (not accessible to the
user) inside the CS5460A. If the amount of energy
that has accumulated in this register over the most
recent A/D sampling period is equal to or greater
than the amount of energy that is represented by
one pulse, the CS5460A will issue a “burst” of one
or more pulses on EOUT (and also possibly on
EDIR). The CS5460A will issue as many pulses as
are necessary to reduce the running energy accu-
mulation value in this register to a value that is less
than the energy represented in one pulse. If the
amount of energy that has been registered over the
most recent sampling period is large enough that it
EOUT
EDIR
P u ls e-R a te R e g is te r P e rio d
16
n
(MCLK / K)
=
fo r In te ge r n
t
t
2
=
x
Positive Energy Burst Negative Energy Burst
. . .
. . .
. . .
. . .
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)