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Summary of Contents for CS5460A

Page 1: ...taneous Pow er IRMS and VRMS for single phase 2 or 3 wire power metering applications The CS5460A interfaces to a low cost shunt resistor or transformer to measure cur rent and resistive divider or potential transformer to measure voltage The CS5460A features a bi directional serial interface for communication with a micro control ler and a pulse output engine for which the average pulse frequency...

Page 2: ...y product information describes products which are in production but for which full characterization data is not yet available Advance product infor mation describes products which are in development and subject to development changes Cirrus Logic Inc has made best efforts to ensure that the information contained in this document is accurate and reliable However the information is subject to chang...

Page 3: ...f Calibration Sequence 41 4 8 9 Is Calibration Required 41 4 8 10 Order of Calibration Sequences 42 4 8 11 Calibration Tips 43 4 9 Phase Compensation 43 4 10 Time Base Calibration Register 44 4 11 Power Offset Register 44 4 12 Input Protection Current Limit 45 4 13 Input Filtering 46 4 14 Protection Against High Voltage and or High Current Surges 50 4 15 Improving RFI Immunity 50 4 16 PCB Layout 5...

Page 4: ...otor Format on EOUT and EDIR 29 Figure 13 Typical Interface of EEPROM to CS5460A 30 Figure 14 Timing Diagram for Auto Boot Sequence 31 Figure 15 CS5460A Auto Boot Configuration Automatic Restart After Power Failure 33 Figure 16 Oscillator Connection 35 Figure 17 VREFOUT Voltage vs Temperature characteristic for a typical CS5460A sample 35 Figure 18 System Calibration of Gain 39 Figure 19 System Ca...

Page 5: ...ut Capacitance IC Zin 1 IC DCLK 4 Note that DCLK MCLK K Parameter Symbol Min Typ Max Unit Accuracy Both Channels Common Mode Rejection DC 50 60 Hz CMRR 80 dB Offset Drift Without the High Pass Filter 5 nV C Analog Inputs Current Channel Maximum Differential Input Voltage Range Gain 10 VIIN VIIN Gain 50 IIN 250 50 mV mV Total Harmonic Distortion THDI 74 dB Common Mode Signal on IIN or IIN Gain 10 o...

Page 6: ...age level on PFMON pin at which the LSD bit can be permanently reset back to 0 without instantaneously changing back to 1 Attempts by the user to reset the LSD bit before this condition is true will not be successful This condition indicates that power has been restored Typically for a given sample the PMHI voltage will be 100mV above the PMLO voltage Parameter Symbol Min Typ Max Unit Dynamic Char...

Page 7: ...ut Output Voltage REFOUT 2 4 2 6 V VREFOUT Temperature Coefficient Note 12 TVREFOUT 25 ppm C Load Regulation Output Current 1 µA Source or Sink VR 6 10 mV Reference Input Input Voltage Range VREFIN 2 4 2 5 2 6 V Input Capacitance 4 pF Input CVF Current 25 nA Parameter Symbol Min Typ Max Unit High Level Input Voltage All Pins Except XIN SCLK and RESET XIN SCLK and RESET VIH 0 6 VD VD 0 5 0 8 VD V V...

Page 8: ...a power supply pin is 50 mA 23 Total power dissipation including all input currents and output currents Parameter Symbol Min Typ Max Unit High Level Input Voltage All Pins Except XIN XOUT SCLK and RESET XIN SCLK and RESET VIH 0 6 VD VD 0 5 0 8 VD V V V Low Level Input Voltage All Pins Except XIN XOUT SCLK and RESET XIN SCLK and RESET VIL 0 48 0 3 0 2 VD V V V High Level Output Voltage except XIN X...

Page 9: ...0 CPUCLK Duty Cycle Note 25 40 60 Rise Times Any Digital Input Except SCLK Note 26 SCLK Any Digital Output trise 50 1 0 100 µs µs ns Fall Times Any Digital Input Except SCLK Note 26 SCLK Any Digital Output tfall 50 1 0 100 µs µs ns Start up Oscillator Start Up Time XTAL 4 096 MHz Note 27 tost 60 ms Serial Port Timing Serial Clock Frequency SCLK 2 MHz Serial Clock Pulse Width High Pulse Width Low t...

Page 10: ...yte Low Byte t t 4 5 SDI Write Timing Not to Scale CS SDO SCLK MSB MSB 1 LSB t 2 t 1 t 8 t 7 SDI MSB MSB 1 LSB Command Time 8 SCLKs LSB t 9 MSB MSB 1 LSB MSB MSB 1 High Byte Mid Byte Low Byte Must strobe SYNC0 command on SDI when reading each byte of data from SDO SDO Read Timing Not to Scale Figure 1 CS5460A Read and Write Timing Diagrams ...

Page 11: ... DS284PP4 11 RES SDI SCLK t 8 t 14 t 13 t 1 1 t 10 SDO CS t 5 t 4 Data from EEPROM Output Output Output Input MODE Input t 12 t 15 t 16 STOP BIT LAST 8 BITS Input t17 Figure 2 CS5460A Auto Boot Sequence Timing ...

Page 12: ...e OWR The OWR can be thought of as the ef fective sample frequency of the voltage channel and the current channel To facilitate communication to a microcontroller the CS5460A includes a simple three wire serial interface which is SPI and Microwire compat ible The serial port has a Schmitt Trigger input on its SCLK serial clock and RESET pins to allow for slow rise time signals 2 1 Theory of Operat...

Page 13: ...egisters are used for cali bration of the device see Section 4 8 Calibration After offset and gain the 24 bit instantaneous data sample values are stored in the Instantaneous Volt age and Current Registers from which the user can read out the data samples via the serial interface 2 1 7 Real Energy and RMS Computations The digital instantaneous voltage and current data is then processed further Ref...

Page 14: ...ve also been multiplied together to pro vide a corresponding instantaneous 24 bit power sample Table 1 conveys the typical relationship between the differential input voltage across the and input pins of the voltage channel input and the corresponding output code in the Instantaneous Voltage Register Note that this table is applicable for the current channel if the current channel s PGA gain is se...

Page 15: ...e CS5460A is calibrated see Calibration the accuracy of the CS5460A with respect to a reference line voltage and line current level on the power mains is not guaranteed to within 0 1 But the linearity of any given sample of CS5460A before calibration will indeed be to within 0 1 of reading over the ranges specified with respect to the input voltage levels required on the voltage and current chan n...

Page 16: ...ate power metering over a very large load range 2 2 2 Single Computation Cycle C 0 Note that C refers to the value of the C bit con tained in the Start Conversions command see Section 3 1 This commands instructs the CS5460A to perform conversions in single com putation cycle data acquisition mode Based on the value in the Cycle Count Register a single computation cycle is performed after the user ...

Page 17: ...de of the power line This means that the common mode potential of the CS5460A will typically oscillate to very high posi tive voltage levels as well as very high negative voltage levels with respect to earth ground poten tial The designer must therefore be careful when attempting to interface the CS5460A s digital out put lines to an external digital interface such as a LAN connection or other com...

Page 18: ...C 10 kΩ 5 kΩ L RShunt V Refer to Input Protection CS5460A Refer to Input Filtering RV RI RI CI ISOLATION 120 VAC Mech Counter Stepper Motor or 22 21 Ω NOTE Current channel input measures voltage just like voltage input CV CI C Vdiff C Idiff Figure 6 Typical Connection Diagram One Phase 2 Wire Direct Connect to Power Line Section 4 12 Section 4 13 VA VD 0 1µF 200µF 200 N 10 Ω 14 VIN 9 VIN IIN 10 15...

Page 19: ...Ω VA Refer to Input Protection R 1 R 2 To Service Refer to Input Filtering RI R I 22 21 Mech Counter Stepper Motor or 1kΩ 1kΩ 120 VAC 120 VAC 240 VAC Serial Data Interface 19 7 23 6 5 20 I Earth Ground C Idiff C Vdiff NOTE Current channel input measures voltage just like voltage input CI C I CV C V CS5460A Figure 8 Typical Connection Diagram One Phase 3 Wire Section 4 12 Section 4 13 VA VD CS5460A...

Page 20: ...the end of the serial port re initialization sequence It can also be used as a NOP command The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command 3 1 3 SYNC1 Command This command is part of the serial port re initialization sequence It can also serve as a NOP command 3 1 4 Power Up Halt If the device is powered down into...

Page 21: ...rforming a system AC offset calibration DC offset calibration AC gain calibration and DC gain calibration The user can calibrate the voltage channel the current channel or both channels at the same time Offset and gain calibrations should NOT be performed at the same time must do one after the other For a given application if DC gain calibrations are performed then AC gain calibration should not b...

Page 22: ...110 Pulse Rate Used to set the energy to pulse ratio on EOUT and EDIR 00111 I Instantaneous Current Register most recent current sample 01000 V Instantaneous Voltage Register most recent voltage sample 01001 P Instantaneous Power Register most recent power sample 01010 E Energy Register accumulated over latest computation cycle 01011 IRMS RMS Current Register computed over latest computation cycle...

Page 23: ... to perform the function For those commands it is important that the correct in formation is written to those registers first 3 3 1 Register Write When a command involves a write operation the serial port will continue to clock in the data bits MSB first on the SDI pin for the next 24 SCLK cycles Command words instructing a register write must be followed by 24 bits of data For in stance to write ...

Page 24: ...nal registers some of which may drive output pins will be reset to their default values on the first MCLK received after detecting a reset event see Table 3 The CS5460A will then assume its active state The term active state as well as the other possible power states of the CS5460A are de scribed in Section 3 6 The reader should refer to Section 5 for a complete description of the registers listed...

Page 25: ...king up the device out of sleep state or stand by state by issuing the Power Up Halt command will also insure that the device is set into active state But remember that in order to send the Power Up Halt command to the device the user must be sure that the serial port has already been or is still initialized Therefore if there are situations in which the user wants to wake the CS5460A out of sleep...

Page 26: ...d put into the CS5460A s Pulse Rate Register call this value PR in order to satisfy this requirement Our first step is to set the voltage and current sensor gain constants KV and KI such that there will be accept able input voltage levels on the inputs when the power line voltage and current levels are at the maximum values of 250 V and 20 A respectively We need to calculate KV and KI in order to ...

Page 27: ...nd current do not determine the appropriate pulse rate setting In stead the maximum line voltage and line current levels must be considered We use the given maxi mum line voltage and line current levels to deter mine KV and KI as previously described to get KV 150 mV 250 V 0 0006 KI 150 mV 20 A 0 0075 Ω where we again have calculated our sensor gains such that the maximum line voltage and line cur...

Page 28: ...uration of the pulses when the Pulse Rate Register is set to MCLK K 1024 The maximum pulse frequency from the EOUT pin is therefore MCLK K 16 When energy is positive EDIR is always high When energy is negative EDIR has the same out put as EOUT When MCLK K is not equal to 4 096 MHz the user can predict the pulse rate by first calculating what the pulse rate would be if a 4 096MHz crystal is used wi...

Page 29: ...ser to insure that pulses will not occur at a rate faster than the 128 ms pulse duration or faster than the mechani cal counter can accommodate This is done by ver ifying that the Pulse Rate Register is set to an appropriate value Because the duration of each pulse is set to 128 ms the maximum output pulse frequency is limited to 7 8 Hz for MCLK K 4 096 MHz For values of MCLK K different than 4 09...

Page 30: ...M must be pro grammed with the user specified commands and register data that will be used by the CS5460A to change any of the default register values if de sired and begin conversions Figure 13 also shows the external connections that would be made to a calibrator device such as a PC or custom calibration board When the metering system is installed the calibrator would be used to control calibrat...

Page 31: ...S5460A during the auto boot sequence The following sequence of user controlled events will cause the CS5460A to execute the auto boot mode initialization sequence A simple timing dia gram for this sequence is shown below in Figure 14 If the MODE pin is set to logic high or if the MODE pin was set tied to logic high dur ing after the CS5460A has been powered on then changing the RESET pin from acti...

Page 32: ...ns In the case of auto boot the CS5460A may be expect ed to reset itself by re executing the Auto Boot se quence whenever the line power is restored Figure 15 shows a reasonably reliable way to con figure the CS5460A s RESET and INT pins so that CS5460A to restart the Auto Boot sequence after a brown out or black out condition This configura tion employs a diode a resistor and a capacitor on the R...

Page 33: ...ts This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that ha ven t been processed yet 4 4 1 2 Typical use of the INT pin The steps below show how interrupts can be han dled by the on board MCU Initialization Step I0 All Status bits are cleared by writing FFFFFF Hex into the Status Register Step I1 The conditional bits which will be used to generate inte...

Page 34: ...the data created by the converter The time out is preprogrammed to approximately 5 sec onds The countdown restarts each time the Energy Register is read Under typical situations the Ener gy Register is read every second As a result the WDT will not time out Other applications that use the watchdog timer will need to ensure that the En ergy Register is read at least once in every 5 second span 4 5 ...

Page 35: ... for operation with a 2 5 V reference between the VREFIN and VA pins A reference voltage must be supplied to the VREFIN pin for proper operation of the two ADCs The CS5460A includes an internal 2 5 V reference available on the VREFOUT pin that can be used as the reference input voltage by connecting the VRE FOUT pin to the VREFIN pin The VREFOUT Temperature Coefficient spec for the on chip voltage...

Page 36: ...Sec tion 4 3 1 Instead of using the VREFOUT Volt age vs Temperature characteristic TEdevice is based on the device s Energy Registration Drift vs Temperature characteristic for any particular CS5460A sample which indicates the drift of the device s energy registration drift over temperature using either the registration of the device s ener gy to pulse engine or the Energy Register Note that typic...

Page 37: ...ction The AC offset registers only affect the results of the rms voltage rms current calculations Referring to Figure 3 the reader should note that there are separate calibration registers for the AC and DC offset corrections for each channel This is not true for gain corrections as there is only one gain register per channel AC and DC gain calibra tion results are stored in the same register The ...

Page 38: ... Specifi cations For the voltage channel the peak differen tial voltage level can never be more than 250 mV The same is true for the current channel if the cur rent channel input PGA is set for 10x gain If the user sets the current channel s PGA gain to 50x then the current channel s input limits are 50 mV Note that for the AC DC gain calibrations there is an absolute limit on the RMS DC voltage l...

Page 39: ...ser should sim ply connect the and pins of the voltage cur rent channels to their ground reference level See Figure 19 The user should not try to run both an offset and gain calibration at the same time This will cause undesirable calibration results 4 8 7 Description of Calibration Algorithms The computational flow of the CS5460A s AC and DC gain offset calibration sequences are illustrated in Fi...

Page 40: ...divided into 0 6 This result is the AC gain calibration re sult stored in the Voltage Channel Gain Register Two examples of AC calibration and the resulting shift in the digital output codes of the channel s in stantaneous data registers are shown in Figures 21 and 22 Note Figure 22 shows that a positive or negative DC level signal can be used even though an AC gain calibration is being executed H...

Page 41: ... contain the default val ues Gains 1 0 DC Offsets 0 0 AC Offsets 0 Although the CS5460A can be used without performing an offset or gain calibration the guar VRMS Register 230 250 x 1 2 0 65054 250 mV 230 mV 0 V 230 mV 250 mV 0 9999 0 92 0 92 1 0000 VRMS Register 0 6000 250 mV 230 mV 0 V 230 mV 250 mV 0 84853 0 84853 Before AC Gain Calibration Vgain Register 1 After AC Gain Calibration Vgain Regis...

Page 42: ... Also note that using gain calibration signal levels which cause the CS5460A to set the internal gain registers to a value that is less than unity will effec tively decrease the guaranteed 0 1 of reading linearity variation range and therefore the accu racy range of the RMS calculation results and the overall energy results Refer to Table 2 This will occur whenever a DC gain calibration is perform...

Page 43: ...into the offset and gain registers of the con verters when power is first applied to the system or when the gain range on the current channel is changed 4 9 Phase Compensation The values of bits 23 to 17 in the Configuration Register can be altered by the user to adjust the amount of time delay that is imposed on the digital ly sampled voltage channel signal This time delay is applied to the volta...

Page 44: ...uitry The user should then adjust the PC 6 0 bits until the Energy Register value is maximized 4 10 Time Base Calibration Register The Time Base Calibration Register notated as TBC in Figure 3 is used to compensate for slight errors in the XIN input frequency External oscil lators and crystals have certain tolerances If the user is concerned about improving the accuracy of the clock for energy mea...

Page 45: ...rmal operating conditions To provide a suitable sensor voltage input level to the voltage channel input pins of the CS5460A the turns ratio of the voltage sense transformer should be chosen such that the ratio is for example on the order of 1000 1 A voltage sense transformer with a 1000 1 turns ratio will provide a 120 mV rms signal to the CS5460A s differential voltage chan nel inputs when the po...

Page 46: ...level on the Vin Iin pins is often set at or very near the CS5460A s common mode ground reference po tential The common mode ground reference po tential is defined by the voltage at the VA pin But this is not required the dc reference level of the Vin Iin pins can be set to any potential be tween VA and VA 250mV In Figure 6 observe the circuitry which has been placed in front of the current channe...

Page 47: ...l suffer an undesirable shift In this situation the real true power energy measurements reported by the CS5460A can con tain significant error because the power factor of the sensed voltage and current signals will be sig nificantly different than the actual power factor of the power line voltage current waveforms Note also that in addition to the time constants of the input R C filters the phase ...

Page 48: ...ations help to improve the ability of both input networks to attenuate very high frequency RFI that can enter into the CS5460A s analog input pins Therefore during layout of the PCB these capacitors should be placed in close proximity to their respective in put pins If any all of the common mode connected capaci tors CV CV CI CI are included in the input networks their values should be selected su...

Page 49: ...anti aliasing filters the sensed voltage signal will be delayed 0 329 µs more than the current signal If we assume that we are metering a 60 Hz power system this implies that the input voltage sense signal will be delayed 0 007 degrees more than the delay imposed on the input current sense sig nal Also we note that when the PC 6 0 bits are set to their default setting of 0000000 the inter nal filt...

Page 50: ... nel input circuitry which can help to protect the CS5460A from being permanently damaged by the surges Referring to Figure 24 the addition of capacitors C1 and C2 can help to further attenuate these high frequency power surges which can greatly decrease the chances that the CS5460A will be damaged Typical values for C1 and C2 may be on the order of 10pF although the exact value is relat ed to the...

Page 51: ...ce of RFI All of these input capacitors C3 C8 should be placed in very close proximity to the and pins of the voltage current input pins in or der to maximize their ability to protect the input pins from high frequency RFI In addition to or as an alternative to these capacitors addition of induc tors L1 L4 can sometimes help to suppress any in coming RFI Note that the additional components just di...

Page 52: ... an analog ground plane with both the VA and DGND pins of the device con nected to the analog plane Note Refer to the CDB5460A Evaluation Board for suggested layout details as well as Applications Note 18 for more detailed layout guidelines Before layout please call for our Free Schematic Review Service ...

Page 53: ...t use all pass filter Otherwise no filter is used default 1 High pass filter is enabled VHPF Control the use of the High Pass Filter on the voltage Channel 0 High pass filter is disabled If IHPF is set use all pass filter Otherwise no filter is used default 1 High pass filter enabled 23 22 21 20 19 18 17 16 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Gi 15 14 13 12 11 10 9 8 EWA Res Res SI1 SI0 EOD DL1 DL0 7 6 5 ...

Page 54: ...ive low level default 01 active high level 10 falling edge INT is normally high 11 rising edge INT is normally low Res Reserved These bits must be set to zero EWA Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire AND us ing an external pull up device 0 normal outputs default 1 only the pull down device of the EOUT and EDIR pins are active Gi Sets the gain of the c...

Page 55: ...e with the system gain when the proper DC input is applied and the Calibration Command is received If AC calibration is performed then after 6N 30 A D conversion cycles where N is the value of the Cycle Count Register the register s is loaded with the system gain when the proper AC input is applied and the Calibration Command is received DRDY will be asserted at the end of the calibration The regi...

Page 56: ... of this register is two s complement notation 5 7 IRMS VRMS Unsigned Output Register Results Address 11 12 These unsigned registers contain the last value of the calculated results of IRMS and VRMS The results are in the range of 0 0 IRMS VRMS 1 0 The value is represented in binary notation with the binary point place to the left of the MSB IRMS and VRMS are output result registers which contain ...

Page 57: ...d and stored so the register may be restored with the desired system offset compensation Note that this register value represents the square of the AC cur rent voltage offset 5 11 Status Register and Mask Register Address 15 Status Register 26 Mask Register Default Binary 00000000000000xxxx000001 Status Register x state depends on device revision Binary 000000000000000000000000 Mask Register The S...

Page 58: ...er being cleared multiple times WDT Watch Dog Timer Set when there has been no reading of the Energy Register for more than 5 seconds MCLK 4 096 MHz K 1 To clear this bit first read the Energy Register then write to the Status Register with this bit set to logic 1 When MCLK K is not 4 096 MHz the time duration is 5 4 096 MHz MCLK K seconds ID3 0 Revision Version Identification EOOR The internal EO...

Page 59: ...to get with MCLK K 4 096 MHz by a factor of 4 096 MHz MCLK K to get the actual pulse rate DRDY Data Ready When running in single computation cycle or continuous computation cycles data acquisition modes this bit will indicate the end of computation cycles When running cal ibrations this bit indicates that the calibration sequence has completed and the results have been stored in the offset or gain...

Page 60: ... respectively This input is a Schmitt trigger to allow for slow rise time signals The SCLK pin will recognize clocks only when CS is low Serial Data Output 6 SDO SDO is the output pin of the serial data port Its output will be in a high impedance state when CS is high Chip Select 7 CS When low the port will recognize SCLK An active high on this pin forces the SDO pin to a high impedance state CS s...

Page 61: ...qual to or above the common mode potential of VA Negative Analog Supply 13 VA The negative analog supply pin must be at the lowest potential Positive Analog Supply 14 VA The positive analog supply is nominally 5 V 10 relative to VA Power Fail Monitor 17 PFMON The power fail Monitor pin monitors the analog supply Typical threshold level PMLO is 2 45 V with respect to the VA pin If PFMON voltage thr...

Page 62: ...sion b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm from lead tips INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0 084 2 13 A1 0 002 0 006 0 010 0 05 0 13 0 25 A2 0 064 0 068 0 074 1 62 1 73 1 88 b 0 009 0 015 0 22 0 38 2 3 D 0 311 0 323 0 335 7 90 8 20 8 50 1 E 0 291 0 307 0 323 7 40 7 80 8 20 E1 0 197 0...

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