CS5460A
DS284PP4
43
calibration levels on the voltage/current inputs)
then the user should next execute the gain calibra-
tions for the voltage/current channels. The user can
execute either the AC or DC gain calibration se-
quences (for each channel).
3. Finally, the user should (if desired) run the AC
offset calibration sequences for the voltage and
current channels. Simply ground the “+” and “-”
inputs of both channels and execute the AC offset
cal sequence.
Note that technically, by following the order of cal-
ibrations as suggested above, if DC offset calibra-
tion is performed for a given channel, and
afterwards a gain calibration is performed on the
channel, then the DC offset register value for the
channel should be scaled by a factor equal to the re-
spective channel’s new gain register value. For ex-
ample, suppose that execution of DC offset
calibration for the voltage channel results in a value
of 0x0001AC = 0.0000510(d) in the Voltage Chan-
nel DC Offset Register (and we assume that the
value in the Voltage Channel Gain Register was at
its default value of 1.000... during execution of this
DC offset calibration). Then if AC or DC gain cal-
ibration is executed for the voltage channel such
that the Voltage Channel Gain Register is changed
to 0x4020A3 = 1.0019920(d), then the user may
want to modify the value in the Voltage Channel
DC Offset Register to 0x0001AD = 0.0000511(d),
which
is
(approximately)
equal
to
1.0019920*0.0000510.
4.8.11 Calibration Tips
To minimize digital noise, the user should wait for
each calibration step to be completed before read-
ing or writing to the serial port.
After a calibration is performed, the offset and gain
register contents can be read and stored externally
by the system microcontroller and recorded in
memory. The same calibration words can be up-
loaded into the offset and gain registers of the con-
verters when power is first applied to the system, or
when the gain range on the current channel is
changed.
4.9 Phase Compensation
The values of bits 23 to 17 in the Configuration
Register can be altered by the user to adjust the
amount of time delay that is imposed on the digital-
ly sampled voltage channel signal. This time delay
is applied to the voltage channel signal in order to
compensate for the relative phase delay (with re-
spect to the fundamental frequency) between the
sensed line-voltage/line-current signals that may be
introduced by the user-supplied voltage and current
sensor circuitry, external to the CS5460A. Voltage
and current transformers, as well as other sen-
sor/filter/protection
devices
deployed
at
the
front-end of the voltage/current sensor networks
can often introduce an ‘artificial’ phase-delay in
the system that distorts/corrupts the phase relation-
ship between the line-voltage and line-current sig-
nals that are to be measured. The user can set the
phase compensation bits PC[6:0] in the Configura-
tion Register to nullify undesirable phase distortion
between the digitally sampled signals in the two
channels. The value in the 7-bit phase compensa-
tion word indicates the amount of time delay that is
imposed on the voltage channel’s analog input sig-
nal with respect to the current channel’s analog in-
put signal.
The default setting of the PC[6:0] bits at pow-
er-on/reset is “0000000”. Note that this setting rep-
resents the smallest time-delay (and therefore the
smallest phase delay) between the voltage- and cur-
rent-channel signal paths. That is, the phase delay
between the voltage/current channels is smallest
with the “0000000” setting. But phase shifts intro-
duced by the designer’s external voltage/current
sensor components may persuade the designer to
intentionally impose a non-zero time-shift correc-
tion value on the voltage channel signal. With the
default setting, the phase delay on the voltage chan-
Summary of Contents for CS5460A
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