CS5460A
40
DS284PP4
the value in the AC offset register is proportional to
the square of the AC offset. First, the inputs should
be grounded by the user, and then the AC offset cal-
ibration command should be sent to the CS5460A.
When the AC offset calibration sequence is initiat-
ed by the user, a valid RMS Voltage Register value
is acquired and squared. This value is then sub-
tracted from the square of each voltage sample that
comes through the RMS data path. See Figure 20.
4.8.7.2 DC Offset Calibration Sequence
The Voltage Channel DC Offset Register holds the
negative of the simple average of N samples taken
while the DC voltage offset calibration was execut-
ed. The inputs should be grounded during DC off-
set calibration. The DC offset value is added to the
signal path to nullify the DC offset in the system.
4.8.7.3 AC Gain Calibration Sequence
The AC voltage gain calibration algorithm attempts
to adjust the Voltage Channel Gain Register value
such that the calibration reference signal level pre-
sented at the voltage inputs will result in a value of
0.6 in the RMS Voltage Register. The user must ap-
ply the ac calibration signal to the “+” and “-” input
pins of the channel under calibration, and the user
must select an appropriate rms level for this cali-
bration signal. During AC voltage gain calibration,
the value in the RMS Voltage Register is divided
into 0.6. This result is the AC gain calibration re-
sult stored in the Voltage Channel Gain Register.
Two examples of AC calibration and the resulting
shift in the digital output codes of the channel’s in-
stantaneous data registers are shown in Figures 21
and 22. Note Figure 22 shows that a positive (or
negative) DC level signal can be used even though
an AC gain calibration is being executed. Howev-
er, an AC signal cannot be used if the DC gain cal-
ibration sequence is going to be executed.
4.8.7.4 DC Gain Calibration Sequence
Based on the level of the positive DC user-provided
calibration voltage that should be applied across
the “+’ and “-” inputs, the CS5460A determines the
Voltage Channel Gain Register value by averaging
the Instantaneous Voltage Register’s output signal
values over one computation cycle (N samples) and
then dividing this average into 1. Therefore, after
the DC voltage gain calibration has been executed,
the Instantaneous Voltage Register will read at
full-scale whenever the DC level of the input signal
is equal to the level of the DC calibration signal that
was applied to the voltage channel inputs during
the DC gain calibration.
For example, if a
+230 mV DC signal is applied to the voltage chan-
nel inputs during the DC gain calibration for the
current channel, then the Instantaneous Voltage
Register will measure at unity whenever a 230 mV
In
M o d u la to r
+
x
to V *, I*, P *, E * R e g is te rs
Filter
N
V R M S
N
Σ
÷
S IN C
D C O ffse t*
G a in *
+
X
2
-X
1
x
N
A C O ffse t*
X
2
0 .6
x
+
+
-
+
2
*
÷
* Denotes readable/writable register
X
N
Figure 20. Calibration Data Flow
Summary of Contents for CS5460A
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