Cirrus Logic CS5460A, Manual

Page: 51 / 64

CS5460A
DS284PP4 51
When such degradation in performance is detected,
the user may improve the CS5460A’s immunity to
RF disturbance by configuring the “+” and “-” in-
puts of the voltage/current channel inputs such that
they are more symmetrical. This is illustrated in
Figure 24 with the addition of resistors R3 and R4,
as well as capacitors C5 and C6. Note that the input
circuitry placed in front of the voltage/current
channel inputs in Figure 24 represents a single-end-
ed input configurations (for both channels). There-
fore, these extra resistors and components may not
necessarily be needed to achieve the simple basic
anti-aliasing filtering on the inputs. However, the
addition of these extra components can create more
symmetry across the ‘+’ and ‘-’ inputs of the volt-
age/current input channels, which can often help to
reduce the CS5460A’s susceptibility to RFI. The
value of C5 should be the same as C3, (and so the
designer may have to re-calculate the desired value
of C3, since the addition of C5 will change the
overall differential-/common-mode frequency re-
sponses of the input filter.) A similar argument can be made for the addition of C6 (to match C8) on the
current channel’s input filter. Finally, addition of
capacitors C4 and C7 can also sometimes help to
improve CS5460A’s performance in the presence
of RFI. All of these input capacitors (C3 - C8)
should be placed in very close proximity to the ‘+’
and ‘-’ pins of the voltage/current input pins in or-
der to maximize their ability to protect the input
pins from high-frequency RFI. In addition to or as
an alternative to these capacitors, addition of induc-
tors L1 - L4 can sometimes help to suppress any in-
coming RFI. Note that the additional components
just discussed can sometimes actually degrade the
CS5460A’s immunity to RFI. The exact configu-
ration that works best for the designer can vary sig-
nificantly, according to the user’s exact PCB
layout/orientation.
Finally, note that inside the
CS5460A, the Vin+, Vin-, Iin+, and Iin- pins have
all been buffered with ~10pF of internal capaci-
tance (to VA-) in attempt to improve the device’s
immunity to external RFI.
VA+ VD+
CS5460A
0.1 µF
100 µF
500
Ω
470 nF
500
Ω
N
10
Ω
14
VIN+
9
VIN-
IIN-
10
15
16
IIN+
PFMON
CPUCLK
XOUT
XIN
RESET
17
2
1
24
19
CS
7
SDI
23
SDO
6
SCLK
5
INT
20
EDIR
22
EOUT
21
0.1 µF
VREFIN
12
VREFOUT
11
VA- DGND
13 4
3
0.1 µF
10 k
Ω
5 k
Ω
L
R
L
4.069 MHz
To Service
1 k
1 k
1 k
1 k
+5 V
+5 V
10 k 10 k 47 k 47 k 20 k 20 k
1 k
SCLK
SDO
CS
INT
SDI
RST
GND
+5 V
5.1 Volt
1 k
120 Vrms
50 50
For Input Surge
Protection
To reduce
EMI susceptibility
D1 D2
D4
D3
R3
R4
C1
C2
R1 R2
R
SHUNT
R5
C4
C5
C6
C7
C3
C8
MODE NC
8
NC
L3
L4
L1
L2
Figure 24. Input Protection for Single-Ended Input Configurations, using resistive divider and current
shunt resistor. Note that the digital interface is isolated using opto-isolators.