Cirrus Logic CS5460A, Manual

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CS5460A
44 DS284PP4
nel signal is ~0.995 µs (~0.0215 degrees assuming
a 60 Hz power signal). Note that the 7-bit phase
compensation word is a 2’s complement binary
number. With MCLK = 4.096 MHz and K=1, the
range of the internal phase compensation ranges
from -2.8 degrees to +2.8 degrees when the input
voltage/current signals are at 60 Hz. In this condi-
tion, each step of the phase compensation register
(value of one LSB) is ~0.04 degrees. For values of
MCLK other than 4.096 MHz, these values for the
span (-2.8 to +2.8 degrees) and for the step size
(0.04 degrees) should be scaled by 4.096 MHz /
(MCLK / K). For power line frequencies other than
60Hz (e.g., 50 Hz), the user can predict the values
of the range and step size of the PC[6:0] bits by
converting the above values to time-domain (sec-
onds), and then computing the new range and step
size (in degrees) with respect to the new line fre-
quency.
Unlike offset/gain calibration, the CS5460A does
not provide an automated on-chip phase calibration
sequence. If the user is concerned about nullifying
artificial phase shift between the voltage-sense and
current-sense signals, the user must determine the
optimal phase compensation setting experimental-
ly. To calibrate the phase delay, the user may try
adjusting the phase compensation bits while the
CS5460A is running in ‘continuous computation
cycles’ data acquisition mode. While the CS5460A
is performing continuous computations, the user
should provide a purely resistive load (no induc-
tance or capacitance) to the power line, such that
nominal-level voltage and current signals from the
power line are sensed into the voltage and current
channels of the CS5460A. In this condition, any
phase delay between the measured voltage and cur-
rent signals is due only to phase delay introduced
by the user’s external voltage/current sensor cir-
cuitry. The user should then adjust the PC[6:0] bits
until the Energy Register value is maximized.
4.10 Time-Base Calibration Register
The Time-Base Calibration Register (notated as
“TBC” in Figure 3) is used to compensate for slight
errors in the XIN input frequency. External oscil-
lators and crystals have certain tolerances. If the
user is concerned about improving the accuracy of
the clock for energy measurements, the Time-Base
Calibration Register value can be manipulated to
compensate for the frequency error. Note from
Figure 3 that the TBC Register only affects the val-
ue in the Energy Register.
As an example, if the desired XIN frequency is
4.096 MHz, but during production-level testing,
suppose that the average frequency of the crystal on
a particular board is measured to actually be
4.091 MHz. The ratio of the desired frequency to
the actual frequency is 4.096 MHz/4.091 MHz =
~1.00122219506. The TBC Register can be set to
1.00122213364 = 0x80280C(h), which is very
close to the desired ratio.
4.11 Power Offset Register
Referring to Figure 3, note the “P
off
” Register that
appears just after the power computation. This reg-
ister can be used to offset system power sources
that may be resident in the system, but do not orig-
inate from the power line signal. These sources of
extra energy in the system contribute undesirable
and false offsets to the power/energy measurement
results. For example, even after DC offset and AC
offset calibrations have been run on each channel,
when a voltage signal is applied to the voltage
channel inputs and the current channel is grounded
(i.e., there is zero input on the current channel), the
current channel may still register a very small
amount of RMS current caused by leakage of the
voltage channel input signal into the current chan-
nel input signal path. Although the CS5460A has
high channel-to-channel crosstalk rejection, such
crosstalk may not totally be eliminated.) The user
can experimentally determine the amount of ‘artifi-
cial’ power that might be induced into the volt-