Cinterion EES3, Hardware Interface Description

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EES3 Hardware Interface Description
6.2 Mounting EES3 onto the Application Platform
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Figure 46:
Recommended stencil design (bottom view)
6.2.1.2 Board Level Characterization
Board level characterization issues should also be taken into account if devising an SMT pro-
cess.
Characterization tests should attempt to optimize the SMT process with regard to board level
reliability. This can be done by performing the following physical tests on sample boards: Peel
test, bend test, tensile pull test, drop shock test and temperature cycling. Sample surface
mount checks are described in
[11] .
It is recommended to characterize land patterns before an actual PCB production, taking indi-
vidual processes, materials, equipment, stencil design, and reflow profile into account. For land
and stencil pattern design recommendations see also
Section 6.2.1.1 . Optimizing the solder
stencil pattern design and print process is necessary to ensure print uniformity, to decrease sol-
der voids, and to increase board level reliability.
Daisy chain modules for SMT characterization are available on request. For details refer to [11] .
Generally, solder paste manufacturer recommendations for screen printing process parame-
ters and reflow profile conditions should be followed. Maximum ratings are described in
Section 6.2.3 .