EES3 Hardware Interface Description
3.14 SPI Interface
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EES3_HD_v01.100b
Page 57 of 118
2009-08-12
Confidential / Released
3.14
SPI Interface
The SPI (serial peripheral interface) is a synchronous serial interface for control and data trans-
fer between the EES3 module and the connected application. Only one application can be con-
nected to the module’s SPI. The interface supports transmission rates up to 6.5 Mbit/s. It
consists of four lines, the two data lines SPIDI/SPIDO, the clock line SPICLK and the chip se-
lect line SPICS.
The EES3 module acts as a single master device, e.g. the clock SPICLK is driven by module.
Whenever the SPICS line is in a low state, the SPI bus is activated and data can be transferred
from the module and vice versa. The SPI interface uses two independent lines for data input
(SPIDI) and data output (SPIDO).
Figure 21:
SPI interface
To configure and activate the SPI bus use the AT^SSPI command. If the SPI bus is active the
two lines I2CCLK and I2DAT are locked for use as I2C lines. Detailed information on the
AT^SSPI command as well explanations on the SPI modes required for data transmission can
be found in
In general, SPI supports four operation modes. The modes are different in clock phase and
clock polarity. The module’s SPI mode can be configured by using the AT command AT^SSPI.
Make sure the module and the connected slave device works with the same SPI mode.
shows the characteristics of the four SPI modes. The SPI modes 0 and 3 are the most
common used modes.
For electrical characteristics please refer to
