CHAPTER 3 THEORY OF OPERATION
3-2
1.2
Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB.
Reset Circuit
Boot + Font ROM (8 MB)
RAM (32 MB)
RAM (DIMM) (max. 128MB)
EEPROM (2048 x 8 bit)
CPU Core
(SPARClite 200MHz)
A S I C
Oscillator 66.6MHz
Address Decoder
DRAM Control
Timer
FIFO
Soft Support
EEPROM I/O
Engine Control I/O
To Engine PCB
Media Gate
Array
BUS
INT
To PC
USB I/O
CDCC Parallel I/O
To PC
Main Program (
3
MB)
STRAGE (1 MB)
AIO Control
NC-6100h
To PC
or Hub
Oscillator 12MHz
Compact
Flash
Fig. 3-2