BONFIGLIOLI Vectron Agile, Communications Manual

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Modbus Agile 43 02/2011
Protocol
7.4 Time Monitoring Function
The Modbus protocol defines a pure Master/Slave operation. If a frequency inverter is addressed by
the bus master, other frequency inverters will only be addressed after the protocol with the first fre-
quency inverter has been completed or the timeout time has expired.
After a frequency inverter has sent a message, a waiting time of 2 ms must be kept. This time is
needed by the frequency inverter in order to switch off the RS485 transmitter. The bus master may
not send a new message until this time has elapsed.
Attention!
If the degree of utilization of the CPU is high (> 90%), the response time can be more than 500 ms.
Note:
The specified times are valid for operation with RS485 and RS232.
8 Handling of Data Sets / Cyclic Writing
Access to the parameter values is carried out on the basis of the parameter number and the required
data set.
There are parameters the values of which exist once (data set 0) as well as parameters the values of
which exist four times (data set 1...4). These are used for data set change-over.
If parameters which exist four times in the data sets are set to data set = 0, all four data sets are set
to the same value.
A read access with data set = 0 to such parameters is only successful if all four data sets are set to
the same value. If this is not the case, error 9 = "different values in data sets" is signaled via the error
register
VABus SST Error Register
11. In this case, you must read out each data set separately for
the relevant parameter (see chapter 7.3.9 "Exception Codes").
New write requests will be blocked by the error register
VABus SST Error Register
11. For this rea-
son, the error register must be read out, i.e. acknowledged, before a new write request can be sent.
Regardless of the signal status of the error register, reading access (read requests) is still possible.
The values are entered into the EEPROM automatically on the controller. If values are to be written
cyclically with a high repetition rate, there must be no entry into the EEPROM, as it only has a limited
number of admissible writing cycles (about 1 million cycles).
Caution!
If the number of admissible writing cycles is exceeded, the EEPROM is destroyed.
In order to avoid the destruction of the EEPROM, data which are to be written cyclically can be en-
tered in the RAM exclusively without a writing cycle on the EEPROM. In this case, the data are vola-
tile, i.e. they are lost when the supply voltage is switched off (Mains Off). They must be written into
the RAM again after the restart (Mains On).
The RAM writing operation is activated by increasing the number of the target data set by five.
Access to the Data Sets of the Frequency Inverter
Parameter EEPROM RAM
Data Set 0 0 5
Data Set 1 1 6
Data Set 2 2 7
Data Set 3 3 8
Data Set 4 4 9
Note:
The Data Sets for parameters
Control Word
410,
Reference Frequency RAM
484 and
Reference
Percentage RAM
524 are always zero. Internally, these are not written to the EEPROM.