
1
2
3
4
5
6
A
B
C
D
6
5
4
3
2
1
D
C
B
A
Title
Number
Revision
Size
Orcad B
Date:
4-Feb-2002
Sheet of
File:
\\Cad 3\c\1 JONS ARCHIVE\8500archive\circuit diagrams\10110077-4\10110077-4.DDB
Drawn By:
MASTER
A[1..19]
D[0..15]
CS[0..3]
C[0..4]
CLK
WATCHDOG
D[0..15]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CS0
CS1
CS2
CS3
RESET
HALT
RESET
HALT
ICTL0
ICTL1
ICTL2
ICTL0
ICTL1
ICTL2
WATCHDOG
CLK
C[0..4]
C0
C1
C2
C3
C4
C0
C1
C2
C3
DELAY
CS[0..3]
C5
C7
C7
FC0
FC1
FC2
AVEC
AVEC
BERR
BERR
BCLR
BCLR
NVHOLD
NVWP
NVHOLD
NVWP
FC1
FRZ
FRZ
FC2
A[1..19]
FC0
SPEN
DELAY
C5
VCC
VCC
VCC
VCC
GND
/ST
7
/RST
6
RST
5
TOL
3
TD
2
/PBRST
1
U1
MAX1232CPA
1
2
JP1
HEADER 2
1
2
3
JP2
3
4
U4B
SN74HC05D
A23
27
A22
26
A21
25
A20
24
A19
22
A18
21
A17
20
A16
19
A15
17
A14
16
A13
15
A12
14
A11
12
A10
11
A9
10
A8
9
A7
8
A6
7
A5
6
A4
5
A3
3
A2
2
A1
1
D15
30
D14
31
D13
32
D12
33
D11
35
D10
36
D9
37
D8
38
D7
40
D6
41
D5
42
D4
43
D3
45
D2
46
D1
47
D0
48
EXTAL
100
XTAL
101
CLKO
98
/RESET
92
/HALT
91
/BERR
94
BUSW
74
DISCPU
73
/FRZ
72
/AS
104
R/~W
103
/UDS-A0
106
/LDS-DS
105
/DTACK
85
/RMC-IOUT1
123
IAC
122
/BCLR
86
/BR
90
/BG
87
/BGACK
88
/IPL0
97
/IPL1
96
/IPL2
95
FC0
132
FC1
130
FC2
129
/AVEC-IOUT0
93
RXD1
52
TXD1
80
RCLK1
82
TCLK1
81
/CTS1
51
/RTS1
79
/DCD1
50
BRG1
76
RXD2-PA0
53
TXD2-PA1
54
RCLK2-PA2
55
TCLK2-PA3
56
/CTS2-PA4
58
/RTS2-PA5
59
/DCD2-PA6
60
BRG2-SDS2-PA7
61
RXD3-PA8
63
TXD3-PA9
64
RCLK3-PA10
65
TCLK3-PA11
66
/CTS3-SPRXD
49
/RTS3-SPTXD
78
/DCD3-SPCLK
77
BRG3-PA12
68
/DREQ-PA13
69
/DACK-PA14
70
/DONE-PA15
71
/IACK7-PB0
108
/IACK6-PB1
109
/IACK1-PB2
110
TIN1-PB3
111
/TOUT1-PB4
113
TIN2-PB5
114
/TOUT2-PB6
115
/WDOG-PB7
117
/CS0-IOUT2
128
/CS1
127
/CS2
125
/CS3
124
PB8
118
PB9
119
PB10
120
PB11
121
U3
MC68302FC16C
R1
1K2
R2
1K2
1
2
U4A
SN74HC05D
GND
R97
10K
VCC
8
U5
12.288MHz
SCC10
SCC11
SCC14
SCC16
SCC20
SCC21
SCC25
SCC26
SCC34
SCC36
SCC20
SCC21
SCC25
SCC24
+ C1
4u7 63V
+
C2
10u 50V
+
C3
10u 50V
+ C4
4u7 63V
GND
VCC
PL3[1..26]
PL312
PL314
PL311
PL313
TXD
DTR
RXD
CTS
CLK
3
D
2
SD
4
CD
1
Q
5
Q
6
U7A
MC74HC74AD
VCC
VCC
1
3
5
7
2
4
6
8
RP1
10K
1
3
5
7
2
4
6
8
RP2
10K
1
3
5
7
2
4
6
8
RP3
10K
1
3
5
7
2
4
6
8
RP4
10K
VCC
1
3
5
7
2
4
6
8
RP5
10K
GND
1
3
5
7
2
4
6
8
RP6
4K7
VCC
R4O
17
R3O
22
R2O
4
R1O
6
T4I
21
T3I
19
T2I
18
T1I
5
T1O
2
T2O
1
T3O
24
T4O
20
R1I
7
R2I
3
R3I
23
R4I
16
C2-
14
C2+
13
V-
15
C1-
12
C1+
10
V+
11
U10
MAX238CNG
1
2
3
4
5
6
7
8
9
10
PL6
HEADER 5X2
GND
DB9 - Recorder
DB25 - RS232
Auxiliary Serial Connector
VCC
VCC
SCC11
SCC10
PULFLW
FLWSIG
+5VA
AGND
CLK
PWMDIVCLK
OVERLOAD_INT
SCC24
SCC24
PWMCLK
4VREF
ANALOGSIG
UPDOWN
PL37
PL39
PL33
PL235
PL121
PL1[1..26]
PL1[1..26]
PL2[1..50]
PL2[1..50]
VCC
GND
Calibrate Protection
SCC12
SCC13
1
3
5
7
2
4
6
8
RP7
10K
SCC12
SCC13
SCC14
SCC16
GND
SCC22
SCC23
SCC22
SCC23
SCC26
1
3
5
7
2
4
6
8
RP8
10K
GND
SCC34
SCC36
PL214
RESET
TEST[0..4]
TEST[0..4]
TEST0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
R3
10K
R4
10K
GND
R5
10K
Output data enable
Output data
Input data
FP[0..2]
FP[0..2]
FP0
FP1
FP2
R8
10K
VCC
GND
Pressure Switch
5
6
U4C
SN74HC05D
8
9
U4D
SN74HC05D
10
11
U4E
SN74HC05D
12
13
U4F
SN74HC05D
CLK
11
D
12
SD
10
CD
13
Q
9
Q
8
U7B
MC74HC74AD
VCC
VCC
GND
R9
4K7
VCC
C4
PL315
VREF
1
+IN
2
-IN
3
GND
4
CS
5
VCC
8
DOUT
6
CLK
7
U11
LTC1286CS8
R11
1K2
R12
4K7
R13
4K7
R14
4K7
VCC
VCC
VCC
VCC
1
2
JP4
HEADER 2
PL3[1..26]
/WP
3
/HOLD
7
SCK
6
SI
5
SO
2
/CS
1
U6
25C020N
SPEN
VCC
ON_24V
ON_24V
VDD
R16
10K
VCC
12
13
U41F
MC74HC14AD
R106
20K
C47
10n
GND
VDD
R107
100R
BAV CONTROLLER TYPE 2
CPU
10110077
4
R108
10K
PL249
SWITCH TO VCC
FORCE FLASH MODE
DTR used to drive
Autozero Valve
ALARMS
ALARMS-4.SCH
CONNECT
CONNECT-4.SCH
ANALOGUE
ANALOGUE-4.SCH
IO
IO-4.SCH
MEMORY
MEMORY-4.SCH
PWM
PWM-4.SCH
S2