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linked together forming an accurate constant-current
source for driving bipolar transistors.
The precise voltage staircase from ICS is injected
into either the non-inverting or inverting input of
DIFFERENTIAL AMPLIFIER IC6, depending on the
position of the two POLARITY reversal switches.
The non-inverting input maintains a negative stair
case for driving PNP transistors, and the inverting
input transposes the polarity for driving
NPN
de
vices. The staircase is then processed by IC6 and
passed through one of the RANGING RESISTORS
selected by the STEP SELECTOR to produce current
steps.
Because transistors have an inherent amount of
turn-on voltage, the current would not be exact if not
accounted for. Therefore, this amount of offset,
called an "error signal" is buffered by ERROR
FEEDBACK BUFFER IC7 and fed back to the opposite
input of IC6. The DIFFERENTIAL AMPLIFIER (IC6)
then strives to maintain the proper amount of cur
rent flowing thru the RANGING RESISTOR by add
ing this error signal to its output. The net result is a
true constant-current flowing into the transistor under
test. regardless of initial base turn-on voltage. The
DC ZERO trimmer R37 is used to zero out the minor
initial offset voltages produced by the IC's them
selves.
In the "Volts per Step" positions of the STEP
SELECTOR. a precision resistor is used to reconvert
the known current steps into exact voltage steps for
testing FET's. RPI is a thick-film resistor network,
contained within a 14 pin Dual In-Line Package (DIP).
It possesses all of the 11 precision resistors used for
current ranging. The processed current or voltage
steps are finally routed through the SOCKET SELEC
TOR to the desired test socket (RIGHT or LEFT).
The higher voltage secondary of the power trans-
former is full-wave rectified by a diode bridge (DI
through D4) to produce a 120Hz "sweep" signal. No
capacitance filtering is used in order to retain fidel
ity of the positive half sine-waves. At this point, the
amplitude is approximately 100 volts peak and is
processed through QI which acts as a series pass
element in conjunction with Q2 and Rl. These de
vices comprise the SWEEP VOLTAGE REGULATOR.
RI is a front panel SWEEP VOLTAGE control which
allows adjustment of the sweep signal from O to
maximum. This scheme also lends itself to addition
of an ELECTRONIC CURRENT LIMITING section,
Q3, in conjunction with RANGING RESISTORS RS
through RS. The range resistors are program.med by
the VERTICAL SENSITIVITY switch to limit the
maximum current available from the SWEEP REG
ULATOR to approximately 130% of the full scale
mA/DIV setting. This limiting feature prevents de
struction of sensitive semiconductors by over dissi
pation.
The POLARITY REVERSAL switch references
either the positive or negative end of the SWEEP
REGULATOR to ground through current-sensing
resistors for testing NPN or PNP transistors. The un
grounded end of the regulator is routed to the col
lector of the transistor under test through SOCKET
SELECTOR SW3 and also to the oscilloscope hori
zontal output terminal.
Sensing resistors R9 through Rl2 are chosen to
produce a constant full-scale voltage value in 4
ranges (selected by VERTICAL SENSITIVITY) to
avoid recalibrating the oscilloscope each time a dif
ferent test current value is desired.
The voltage signal representing the current which
appears across the sensing resistors is processed
through INVERTING BUFFER IC8 to produce curves
as normally displayed throughout the industry.
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