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Operation
Operating Instructions Option Module IEI for b maXX drive PLC BM4-O-
IEI-01
35
7
7.2
Configuring the IEI option module in the application program
Depending on the mode, the IEI option module uses an internal register to count the sig-
nal edges (or increments) of the rectangle incremental encoder or the edges of a 24 V
signal.
For the contents of this register to be copied synchronously to the b maXX drive PLC into
communication RAM, you must set a trigger source. In the case of the IEI option module,
signal SYNC1 from the BACI is set as the trigger source (this signal is latch condition 1).
On the b maXX drive PLC, you must ensure that this signal is available in the b maXX
(see
Synchronizing the IEI option module with the b maXX drive PLC
At configuration of the IEI option module, you must make the following settings in depen-
dence on the mode:
m
encoder mode
n
selection of multiplication of the encoder signal (single, double, quadruple)
n
selection of latch condition 2
n
selection of latch condition 3
n
selection of the rectangle incremental encoder's direction of rotation
m
Probe mode
n
Selection of the edge of the 24 V signal that is to be evaluated
n
Selection of the direction of counting (up/down)
FB IEI_INIT from library IEI_PLC01_20bd00 (PROPROG wt II) or IEI_PLC01_30bd00
(ProProg wt III) or above is available for configuring encoder mode or probe mode (see
Using FB IEI_INIT, you set or select:
m
encoder mode
n
multiplication of the encoder signal (single, double, quadruple)
n
the direction of rotation of the rectangle incremental encoder
or
m
Probe mode
n
the edge of the 24 V signal that is to be evaluated.
The system sets the direction of counting externally via a signal at input "probe 2".
If the signal at input "probe 2" is logically FALSE or physically LOW, the internal
counter counts up.
If the signal at input "probe 2" is logically TRUE or physically HIGH, the internal
counter counts down.
In encoder mode, you must additionally set latch conditions 2 and 3 for taking the value
of the internal counter in counter latch registers 2 and 3. This is carried out via the latch
mode register (see