Operation
Operating Instructions Option Module IEI for b maXX drive PLC BM4-O-
IEI-01
47
7
Bit 12 - Signal edge for latch condition 3:
Using bit 10, you choose which signal edge of the released and ANDed signals from bit
8 to bit 11 the system must detect for latch condition 3 to be met.
Bit 13 to bit 15 are reserved.
Example latch mode register:
Latch condition 2 is the rising edge of probe 1. Latch condition 3 is the falling edge of
probe 1:
The value 16#1101 is entered in the latch mode register
(*.w_LATCH_MODE = 16#1101).
After activating the IEI option module, the latch mode register has the value 16#0000, i.e.
no latch condition 2 and no latch condition 3 are selected.
7.3.11 Counter mode register
Using counter mode register *.w_COUNTER_MODE, you set the mode of the IEI option
module.
m
Encoder mode with
n
Single multiplication of the encoder signal,
n
Double multiplication of the encoder signal, or
n
Quadruple multiplication of the encoder signal,
m
Probe mode with
n
Counting of the rising and falling edge of the 24 V signal that is connected at
probe 1.
n
Counting of the rising edge of the 24 V signal that is connected at probe 1.
Reserv
ed
Falling signal
edge for
latc
h condition 3
En
code
r zer
o
tr
ack n
o
t
a
s
la
tc
h co
nd
itio
n 3:
Re
fe
re
nc
e c
am
n
o
t
a
s
la
tc
h co
nd
itio
n 3:
Pr
ob
e 2 not as
latch
co
ndition
3:
Pr
ob
e 1 as
latch
co
ndition
3:
Reserv
ed
Rising
sign
al ed
ge for
latc
h condition 2
En
code
r zer
o
tr
ack n
o
t
a
s
la
tc
h co
nd
itio
n 2:
Re
fe
re
nc
e c
am
n
o
t
a
s
la
tc
h co
nd
itio
n 2:
Pr
ob
e 2 not as
latch
co
ndition
2:
Pr
ob
e 1 as
latch
co
ndition
2:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Binary
value
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
Hexadeci-
mal value
1
1
0
1
16#1101