|
- Revised,
||
- New
SCHEMATICS
©2003 BALLY GAMING AND SYSTEMS
14-11
ProSlot-
6000
™
1N4148
TRACE
NOT USED
JW19
!WDRST
13
12
!RESET
74HC08
U71D
!RES_REQ
1M
ANTENNA
ANT1
EXT_ANT
JW1
R54
R55
P2_
A
15
+5
!WDRST
+
10V
10uF
C17
.1uF
C18
Q14
Q13
74HC4060
Q12
Q10
3
U72
9
11
74HC04
U73D
8
1M
TP8
FF101E
R74
12
11
RST
PI
!RES_REQ
470K
R75
PO
10
PO
2
9
3
540ms
6
1
15
13
Q9
14
Q8
Q7
4
Q6
5
Q5
7
Q4
74HC05
100pF
C16
11
10
U56E
74HC04
U73B
4
9
74HC05
U56D
8
2
3
R61
1N4148
CR2
24K
47K
R52
470pF
C12
1N4148
CR3
CR4
1N4148
+5
47K
R51
+5
470K
+5
R53
8
RESET
SW4
TLC372C
U75A
4
+
1
-
!RESIN
4.7K
R62
+5
BP3
!RESIN
.1uF
1%
1.13K
R69
SENSE
TL7702A
3
CT
2
RESIN
REF
1
RESET
RESET
5
6
U77
7
1%
1.00K
R71
2K
R70
+5
LED1
74HC05
74HC05
U56B
2.2K
R72
3
R76
270
4
!RESET
TP4
+5
U56C
5
!RESET
!HALT
6
!HALT
!R_W
A23
A22
P2_B26
D4
R_W
!R_W
P2_B[1..40]
D[0..15]
A[0..23]
P
2_A
[1
..40]
P2_A[1..40]
P2_B[1..40]
A[0..23]
D[0..15]
D0
D3
D1
D2
D6
D5
D7
D8
D12
D9
D11
D10
VSS
GND
VDD
VCC
+5
D14
D15
D13
A2
A1
A3
A4
A6
A5
A8
A7
2
1
A16
./PAGE5.SCH
./PAGE4.SCH
./PAGE3.SCH
./PAGE2.SCH
./LINK
A12
A10
A9
A11
A13
A15
A14
3
4
5
1
1
1
A19
A18
A17
A20
A21
RP33
10K
!SYSTEM_RESET
DM14
59
8
!LDS
!LDS
!ADC_INT
!ADC_CS
15
DM4
5
U57A
74HC02
U73E
74HC04
A[0..23]
10
11
!ADC_CS
3
R_W
2
74HC245
11
B8
12
13
14
B7
B6
B5
B4
DM0
DM1
DM3
DM2
!R_W
9
19
1
DIR
G
A8
8
A7
7
A6
6
A5
A4
1
R_W
!ADC_CS
74HC04
5
6
U61C
R_W
!R_W
B3
A3
74HC245
16
17
18
B3
B2
B1
U22
11
B8
12
13
14
15
B7
B6
B5
B4
DM7
DM5
DM6
4
A3
3
A2
2
A1
DM12
DM8
DM10
DM9
DM11
!R_W
9
19
1
DIR
G
A8
8
A7
7
A6
6
A5
5
A4
16
17
18
B2
B1
U23
74HC244
2Y1
1Y4
1Y3
1Y2
1Y1
12
14
16
18
2Y2
2Y4
2Y3
7
9
3
5
DM14
DM15
DM13
4
3
A2
2
A1
AM6
AM4
AM5
AM3
AM1
AM2
AM8
AM7
2A1
1A4
1A3
1A2
1A1
8
6
4
2
2A2
2A4
2A3
13
11
17
15
D6
D5
D7
D4
D2
D3
D0
D1
2
D
M
[0..15]
1
RP34
10K
3
1
14
+5
1
DM15
4
NOT STUFFED
74HC74
U76A
3
1
CLK
CL
6
Q
2
PR
D
4
5
Q
!ADC_CS
R_W
AGND
INTR
ADC0804
5
8
3
2
1
WR
RD
CS
VREF
CLK
10K
150pF
C21
9
R82
R63
R_W
!ADC_CS
22K
R56
Q36
2N3904
22K
20M
R65
R64
JW16
GND
SHLD
CLR
DB3
12
13
14
11
DB4
DB7
DB6
DB5
15
16
17
18
DB2
DB1
DB0
VI-
CLKR
VI+
U59
29.4912MHZ
19
7
6
VCC
74HC161
R19
OUT
VCC
Y1
8
7
4.7K
68HC000FN16
D15
D14
58
4
1
9
2
10
7
6
5
LOAD
CLK
ENT
ENP
D
C
B
RCO
QD
QC
QB
3
MR_W
+5
9
R/W
LDS
A
U36
QA
VBB
2N3905
Q37
CR5
1N4148
CR6
1N4148
D5
13
15
11
12
14
14.7456_MHZ
7.37_MHZ
1.84_MHZ
3.69_MHZ
150
R57
+12
MR_W
2Y4
2A4
3
AM16
17
U65
74HC244
12
1Y2
1Y1
1Y4
1Y3
16
18
14
2Y4
2Y3
2Y2
2Y1
5
7
9
2G
1G
19
1
AM10
AM9
AM14
AM15
AM12
AM13
AM11
8
1A2
1A1
1A4
1A3
4
2
6
2A4
2A3
2A2
2A1
15
13
11
U64
14
74HC244
1Y3
1Y2
1Y1
16
18
2Y3
2Y2
2Y1
1Y4
5
7
9
12
2G
1G
19
1
AM22
AM18
AM23
AM17
AM19
AM20
AM21
6
1A3
1A2
1A1
4
2
2A3
2A2
2A1
1A4
15
13
11
8
AM22
DM10
DM13
DM12
DM11
DM8
DM7
DM6
DM9
DM1
DM3
DM4
DM5
DM2
AM23
DM0
A
M
[1
..23]
AM13
AM19
AM21
AM18
AM20
AM15
AM17
AM14
AM16
AM9
AM12
AM10
AM11
AM5
AM8
AM7
AM6
U63
3
!RESET
2G
1G
19
1
17
AM3
AM4
AM1
AM2
A4
IPL0
IPL0
54
RESET
D5
63
D13
D12
D11
D10
60
61
62
D9
D8
D7
D6
64
65
66
67
4
D4
D3
D2
D1
2
68
1
3
D0
A23
A22
5
55
!HALT
!AS
!UDS
!RESET
19
20
7
6
UDS
AS
HALT
DTACK
BGACK
44
A17
A21
A20
A19
A18
53
51
50
49
A13
A16
A15
A14
48
47
46
45
40
A12
A11
A10
A9
43
42
41
A8
A7
A6
A5
39
38
37
36
30
FC0
FC1
!VMA
E
FC2
BG
22
21
E
VMA
28
29
11
FC0
FC2
FC1
!BERR
IPL2
!DTACK
IPL1
13
24
10
BERR
BR
12
25
26
IPL2
IPL1
74HC04
U73F
13
TP3
12
10K
!AS
!UDS
VMA
VMA
+5
+5
RP27I
1
10
6
4
RP28
1
1
10K
E
IPL1
IPL2
A3
A2
A1
35
34
33
32
U31
14.7456_MHZ
!VPA
IPL0
27
23
15
VPA
CLK
DTACK CONTROL PAL
SMART I/O DECODER
12
11
!WDRST
5
6
+5
TLC372C
U75B
7
74HC10
U48B
!RESET
7
1
10K
RP27F
+5
14.7456_MHZ
10K
4
RP27C
1
+5
!DTACKB
!DTACKA
!DTACKC
!DTACKB
!DTACKA
!DTACKC
!DTACK
10K
10K
2
RP28A
RP28B
1
FCA0
4
IODEC
FCA1
AS
5
74HC04
U61F
!AS
13
12
3
C
!VPA
!IACK
AS
3
1
+5
!IODTACK
14.7456_MHZ
!DTACKA#B#C
FEEDBACK_IN
!LOCIO
!UDS
!IACK
!VPA
AS
I5
!LDS
I9
16V8
7
11
9
8
I8
I7
I6
2
6
5
4
3
I4
I3
I2
I1
1
I0
U62
A8
!LOCIO
!DTACK
!IODTACK
G2A
5
G2B
4
6
G1
6
!AS
AS*FCA0*IODEC
18
16
AS*FCA0*IODEC
A11
A7
A6
A5
A10
A9
FCA1
U48A
74HC10
13
3
2
1
A
B
U58
74HC154
2
1
19
G2
G1
12
15
14
17
SIMPLE I/O DECODER
A4
A3
A1
A2
D
20
21
22
23
C
B
A
9
13
12
11
10
15
14
13
11
8
7
6
5
10
9
8
7
U32
2
4
3
2
1
6
5
4
3
0
1
CPU/RESET/CLOCK/BATTERY
Y2
!EXP_CS
F5
13
12
F6
F7
!WDRST
FEEDBACK_OUT
A8
A7
A6
!WAIT_STATE
18
17
16
15
14
F1
F2
F3
F4
19
F0
!DTACK
74HC138
Y6
Y7
7
Y5
Y4
Y3
10
11
12
9
!SOUND
!ADC_CS
!VIACS2
!VIACS1
!DUARTCS3
DECODING
!SROPEN
1
Y0
Y1
13
14
15
74HC02
!DUARTCS2
!DUARTCS1
U57D
!WDRST
13
74HC04
U61A
2
INPUT PORT 1
INPUT REEL SENSE
INPUT PORT 0
OUTPUT REEL PORT
!IO_CS2
!IO_CS1
!I2C
OUTPUT PORT 3
OUTPUT PORT 2
OUTPUT PORT 1
OUTPUT PORT 0
R_W
R_W
74HC32
74HC32
U33A
1
2
3
13
12
!RLSEN
!IP1
!IP0
!IO_CS2
!IO_CS1
!RLDRV
U33D
11
!OP3
!EXP_CS
!UDS
!LDS
!DUARTCS3
!VIACS1
!VIACS2
!SOUND
!DUARTCS2
!DUARTCS1
!SROPEN
!IO_CS2
!IP1
!RLSEN
!IP0
!I2C
!IO_CS1
!RLDRV
!OP3
!OP2
INTERRUPT CONTROL PAL
ROM SMI CHIP SELECT
ROM MAINS CHIP SELECT
SAFE RAM CHIP SELECT
RAM CHIP SELECT
LOCAL I/O DECODER
I/O PORT DECODER
!LDS
REEL5_S1
!UART1
!UART3
!AC_FAIL
AA SIZE
1500 mAH
3.5V
BATT1
JW20
A[0..23]
IODEC
!VIA1
!VIA2
!UART1
!UART3
!VIA2
!RESET
!VIA1
10
7
5
1K
R66
+5
7.37_MHZ
1.84_MHZ
3.69_MHZ
10K
RP28
1
1
1
+5
MR_W
FC0
FC2
FC1
9
11
10
!AS
1
23
!WAIT_STATE
!UART1
!UART3
!VIA2
!IACK
!RESET
!VIA1
!ACFAIL
A1
A3
A2
R_W
!ADC_CS
!VPA
!LOCIO
IODEC
IRQ (IPL6)
IRQ (IPL3)
IRQ (IPL1)
AC FAIL (IPL7)
IRQ (IPL4)
I9
O9
22V10
I11
I12
I10
13
11
10
O10
14
5
9
8
I8
7
I7
6
I6
I5
I1/CLK
4
I4
3
I3
2
I2
19
O8
O7
O6
O5
15
16
17
18
O4
O3
O2
O1
20
21
22
ADDRESS DECODE PAL
A14
A18
A16
A17
A15
A21
A22
A20
A19
8
74HC10
U48C
!IACK
A23
A12
A13
I3
O3
13
22V10
I12
8
11
10
9
7
6
5
4
I11
I10
I9
I8
I7
I6
I5
I4
U46
16
14
15
O10
O9
O8
17
18
19
20
O7
O6
O5
O4
U60
3
2
1
I2
I1/CLK
!RLSEN
21
22
23
O2
O1
!AS
!UDS
FC0
!DTACK
FC1
FC2
REEL5_S2
REEL5_S1
2A4
!RLSEN
REEL5_S2
19
2G
1
1G
MR_W
S2
S1
FC2
FC1
FC0
8
2A3
2A2
2A1
1A4
13
17
15
11
1A3
1A2
6
4
2
1A1
2Y4
74HC244
U47
12
7
3
5
9
2Y3
2Y2
2Y1
1Y4
14
16
18
1Y3
1Y2
1Y1
R_W
D10
D9
D8
D11
REEL5_S1
!ROM_SMI_CS
!ROM_MAINS_CS
!Z_CROSS
!Z_CR_REL
DUART3 IACK
!IACKD3
R_W
R_W
DUART 2 IRQ (IPL2)
ZERO CROSS RELEASE
DUART1 IACK
DUART2 IACK
8.3ms IRQ (IPL5)
!VPA
IPL2
IPL1
IPL0
74HC32
4
74HC32
U33C
10
9
8
5
U33B
6
!OP1
!UART2
IPL2
!Z_CR_REL
!IACKD1
!IACKD2
Z_CROSS
IPL1
IPL0
!UART2
IPL2
!IACKD2
!IACKD1
!IACKD3
IPL1
IPL0
!AS
S[1..8]
!ROM_MAINS_CS
!ROM_SMI_CS
!SRCS
!LOCIO
IODEC
!RAMCS
!SRCS
!RAMCS
S[1..8]
!OP1
!OP0
REEL5_S2
D[0..15]
Card Rack / MPU Board
MPU Board (1 of 5) AS-03356-0438
;
;
;
;
;
ESlant
;
;
;
;
;
Upright
;
;
;
;
;
Slant
Summary of Contents for ProSlot 6000
Page 50: ...2003 Bally Gaming and Systems 3A 4 Glass and Decals Revised New...
Page 122: ...2003 Bally Gaming and Systems 3B 4 ProSlot 6000 Revised New...
Page 246: ...2003 Bally Gaming and Systems 3 100 ProSlot 6000 Revised New...
Page 250: ...Periodic Maintenance 4 4 2002 Bally Gaming and Systems...
Page 274: ...GLOSSARY 5 20 2002 Bally Gaming and Systems...
Page 278: ...6B 4 2000 Bally Gaming Inc ProSlot 6000 Plus...
Page 290: ...6B 16 2000 Bally Gaming Inc ProSlot 6000 Plus Tower Selections...
Page 291: ...6B 17 2000 Bally Gaming Inc ProSlot 6000 Plus Tower Selections cont...
Page 294: ...6B 20 2000 Bally Gaming Inc ProSlot 6000 Plus...
Page 304: ...Peripherals 8 4 2002 Bally Gaming and Systems...
Page 348: ...Peripherals 8 48 2002 Bally Gaming and Systems...
Page 396: ...Revised New 2003 BALLY GAMING AND SYSTEMS 9 48 ProSlot 6000...
Page 400: ...12 4 ProSlot 6000 MARCH 2000...
Page 404: ...12 8 ProSlot 6000 MARCH 2000...