TROUBLESHOOTING
DIAGNOSTIC DIPSWITCH SELECTION
I-E96-322A
6 - 3
Figure 6-2. Diagnostic Dipswitch Settings
HSS MODULE ADDRESS
TEST ID
HALT ON ERROR (ON = DISABLED, OFF = ENABLED)
TP25415A
OFF = PASS/FAIL, ON = TEST NUMBER DISPLAY
DIAGNOSTIC MODE (OFF = ENABLED, ON = DISABLED)
ON
ON
OFF
OFF
S1
S2
1
1
2
2
3
3
4
4
5
5
MSB
6
6
7
7
8
8
LSB
UN
US
E
D
UN
US
E
D
Table 6-1. Diagnostic Test ID Numbers and Dipswitch S2 Settings
Test Name
ID
Dipswitch S2 Pole
1
Description
1
2
2
3
3
4
5
6
7
8
Dipswitch and
LED test
00
x
y
0
0
0
0
0
0
Increments a count on the LEDs until all are
illuminated. The status LED displays a logical
and mathematical manipulation of the bytes
on dipswitches S1 through S4. Off indicates
even parity, green indicates odd parity.
Watchdog
timer test
01
x
y
0
0
0
0
0
1
The watchdog timer is started. An error code
displays if it does not expire in 15 secs.
ROM test
02
x
y
0
0
0
0
1
0
Verifies the checksum of the EPROM.
SRAM test
03
x
y
0
0
0
0
1
1
Performs a walking ones and zeros test on the
static RAM.
Timer test
04
x
y
0
0
0
1
0
0
Initializes the timer and checks its operation.
DPRAM test
05
x
y
0
0
0
1
0
1
Performs a walking ones and zeros test on
dual port RAM.
A/D reference
test
06
x
y
0
0
0
1
1
0
Checks internal analog-to-digital reference
voltages.
Output D/A test
07
x
y
0
0
0
1
1
1
Checks analog output voltages of the 12-bit D/
A converter.
Position D/A
test
08
x
y
0
0
1
0
0
0
Checks analog output voltages of the 16-bit D/
A converter.
Group test
(02-08)
09
x
y
0
0
1
0
0
1
Performs tests 2 through 8 in numerical order.
NOTES:
1. 0 = ON or CLOSED, 1 = OFF or OPEN.
2. X = selects LED display mode. See Figure 6-2 for pole 1 settings.
3. Y = selects halt on error or continuously loop the tests. See Figure 6-2 for pole 2 settings.
