74
ATmega161(L)
1228B–09/01
• Bit 0
–
MPCM0/MPCM1: Multi-processor Communication Mode
This bit is used to enter Multi-processor Communication Mode. The bit is set when the
slave MCU waits for an address byte to be received. When the MCU has been
addressed, the MCU switches off the MPCMn bit and starts data reception.
For a detailed description, see “Multi-processor Communication Mode”.
UART0 Control and Status
Registers – UCSR0B
UART1 Control and Status
Registers – UCSR1B
• Bit 7
–
RXCIE0/RXCIE1: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 6
–
TXCIE0/TXCIE1: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 5
–
UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART
Data Register Empty interrupt routine to be executed, provided that global interrupts are
enabled.
• Bit 4
–
RXEN0/RXEN1: Receiver Enable
This bit enables the UART receiver when set (one). When the receiver is disabled, the
TXCn, ORn and FEn status flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3
–
TXEN0/TXEN1: Transmitter Enable
This bit enables the UART transmitter when set (one). When disabling the transmitter
while transmitting a character, the transmitter is not disabled before the character in the
shift register plus any following character in UDRn has been completely transmitted.
• Bit 2
–
CHR90/CHR91: 9-bit Characters
When this bit is set (one), transmitted and received characters are nine bits long, plus
start and stop bits. The ninth bit is read and written by using the RXB8n and TXB8 bits in
UCSRnB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
• Bit 1
–
RXB80/RXB81: Receive Data Bit 8
When CHR9n is set (one), RXB8n is the ninth data bit of the received character.
• Bit 0
–
TXB80/TXB81: Transmit Data Bit 8
When CHR9n is set (one), TXB8n is the ninth data bit in the character to be transmitted.
Bit
7
6
5
4
3
2
1
0
$0A ($2A)
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
CHR90
RXB80
TXB80
UCSR0B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
1
0
Bit
7
6
5
4
3
2
1
0
$01 ($21)
RXCIE1
TXCIE1
UDRIE1
RXEN1
TXEN1
CHR91
RXB81
TXB81
UCSR1B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
1
0