48
ATmega161(L)
1228B–09/01
disturb an OCR2 write in progress. To detect that a transfer to the destination
register has taken place, a Asynchronous Status Register – ASSR has been
implemented.
•
When entering Power-save mode after having written to TCNT2, OCR2 or TCCR2,
the user must wait until the written register has been updated if Timer/Counter2 is
used to wake up the device. Otherwise, the MCU will go to sleep before the
changes have had any effect. This is extremely important if the Output Compare2
interrupt is used to wake up the device; output compare is disabled during write to
OCR2 or TCNT2. If the write cycle is not finished (i.e., the MCU enters sleep mode
before the OCR2UB bit returns to zero), the device will never get a compare match
and the MCU will not wake up.
•
If Timer/Counter2 is used to wake up the device from Power-save mode,
precautions must be taken if the user wants to re-enter Power-save mode: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and
re-entering Power-save mode is less than one TOSC1 cycle, the interrupt will not
occur and the device will fail to wake up. If the user is in doubt whether the time
before re-entering Power-save is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
1.
Write a value to TCCR2, TCNT2, or OCR2.
2.
Wait until the corresponding Update Busy flag in ASSR returns to zero.
3.
Enter Power-save mode.
•
When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter2
is always running, except in Power-down mode. After a Power-up Reset or wake-up
from power-down, the user should be aware of the fact that this oscillator might take
as long as one second to stabilize. The user is advised to wait for at least one
second before using Timer/Counter2 after power-up or wake-up from power-down.
The contents of all Timer/Counter2 registers must be considered lost after a wake-
up from power-down, due to unstable clock signal upon start-up, regardless of
whether the oscillator is in use or a clock signal is applied to the TOSC pin.
•
Description of wake-up from Power-save mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake-up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at
least 1 before the processor can read the counter value. The interrupt flags are
updated three processor cycles after the processor clock has started. During these
cycles, the processor executes instructions, but the interrupt condition is not
readable and the interrupt routine has not started yet.
•
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is
therefore advanced by at least 1 before the processor can read the timer value,
causing the setting of the interrupt flag. The output compare pin is changed on the
timer clock and is not synchronized to the processor clock.
