86
ATmega161(L)
1228B–09/01
Using the External
Memory Interface
The interface consists of:
Port A: multiplexed low-order address bus and data bus
Port C: high-order address bus
The ALE pin: address latch enable
The RD and WR pin: read and write strobes
The external memory interface is enabled by setting the external SRAM enable bit
(SRE) of the MCU control register (MCUCR) and will override the setting of the data
direction registers DDRA, DDRD and DDRE. When the SRE bit is cleared (zero), the
external memory interface is disabled and the normal pin and data direction settings are
used. When SRE is low, the address space above the internal SRAM boundary is not
mapped into the internal SRAM, as in AVR parts do not have an external memory
interface.
When ALE goes from high to low, there is a valid address on Port A. ALE is low during a
data transfer. RD and WR are active when accessing the external memory only.
When the external memory interface is enabled, the ALE signal may have short pulses
when accessing the internal RAM, but the ALE signal is stable when accessing the
external memory.
Figure 55 sketches how to connect an external SRAM to the AVR using eight latches
that are transparent when G is high.
Figure 55.
External SRAM Connected to the AVR
For details on the timing for the SRAM interface, please see Figure 84 through Figure 87
and Table 51 through Table 58.
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
D
Q
G
Port A
ALE
Port C
RD
WR
AVR