Atmel ATmega161 Manual Download Page 143

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143

ATmega161(L)

1228B–09/01

Notes:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work
with registers $00 to $1F only.

Summary of Contents for ATmega161

Page 1: ...ded 16 bit Timer Counter System with Separate Prescaler Compare Capture Modes and Dual 8 9 or 10 bit PWM Dual Programmable Serial UARTs Master Slave SPI Serial Interface Real time Counter with Separate Oscillator Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Special Microcontroller Features Power on Reset and Programmable Brown out Detection External and In...

Page 2: ...T2 PE1 ALE PE2 OC1B PC7 A15 PC6 A14 PC5 A13 PC4 A12 PC3 A11 PC2 A10 PC1 A9 PC0 A8 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 MOSI PB5 MISO PB6 SCK PB7 RESET RXD0 PD0 NC TXD0 PD1 INT0 PD2 INT1 PD3 TOSC1 PD4 OCIA TOSC2 PD5 PA4 AD4 PA5 AD5 PA6 AD6 PA7 AD7 PE0 ICP INT2 NC PE1 ALE PE2 OC1B PC7 A15 PC6 A14 PC5 A13 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 WR PD6 RD ...

Page 3: ...able Watchdog Timer with internal oscillator an SPI serial port and 3 soft ware selectable power saving modes The Idle mode stops the CPU while allowing the SRAM timer counters SPI port and interrupt system to continue functioning The Power down mode saves the register and SRAM contents but freezes the oscillator dis abling all other chip functions until the next external interrupt or hardware res...

Page 4: ...0 PC7 PORTD DRIVERS PD0 PD7 DATA DIR REG PORTD DATA REGISTER PORTB PORTB DRIVERS PORTE DRIVERS PE0 PE2 DATA REG PORTE DATA DIR REG PORTE PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTER SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER COUNTERS INSTRUCTION DECODER TIMING AND CONTROL OSCILLATOR INTERRUPT UNIT EEPROM STATUS REGISTER Z Y X AL...

Page 5: ...urce current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running Port C also serves as an address high output when using external memory interface Port D PD7 PD0 Port D is an 8 bit bi directional I O port with internal pull up resistors The Port D output buffers can sink 20 mA As inputs Port D pins that are ex...

Page 6: ...hip oscillator as shown in Figure 2 Either a quartz crystal or a ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3 Figure 2 Oscillator Connections Figure 3 External Clock Drive Configuration XTAL2 XTAL1 GND C2 C1 XTAL2 XTAL1 GND NC EXTERNAL OSCILLATOR SIGNAL ...

Page 7: ...ss pointer for the constant table look up func tion These added function registers are the 16 bit X register Y register and Z register The ALU supports arithmetic and logic functions between registers or between a con stant and a register Single register operations are also executed in the ALU Figure 4 shows the ATmega161 AVR RISC microcontroller architecture Figure 4 The ATmega161 AVR RISC Archit...

Page 8: ...om the program memory This concept enables instructions to be executed in every clock cycle The pro gram memory is Self programmable Flash memory With the jump and call instructions the whole 8K word address space is directly accessed Most AVR instructions have a single 16 bit word format Every program mem ory address contains a 16 or 32 bit instruction During interrupts and subroutine calls the r...

Page 9: ... interrupt vector in the interrupt vector table at the beginning of the program memory The different interrupts have priority in accordance with their interrupt vector position The lower the interrupt vector address the higher the priority 32 Gen Purpose Working Registers 64 I O Registers Internal SRAM 1024 x 8 0000 001F 005F 0060 045F 0020 000 1FFF Data Memory Program Memory Program Flash 8K x 16...

Page 10: ...assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although not being phys ically implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z registers can be set to index any register in the file The X register Y register and Z register The registers R26 R31 have some added funct...

Page 11: ...ontains 16K bytes of On chip Self programmable and In System Pro grammable Flash memory for program storage Since all instructions are 16 or 32 bit words the Flash is organized as 8K x 16 The Flash memory has an endurance of at least 1 000 write erase cycles The ATmega161 program counter PC is 13 bits wide thus addressing the 8 192 program memory locations See page 108 for a detailed description o...

Page 12: ... WR are inactive during the whole access cycle External memory operation is enabled by setting the SRE bit in the MCUCR register See Interface to External Memory on page 82 for details Accessing external memory takes one additional clock cycle per byte compared to access of the internal SRAM This means that the commands LD ST LDS STS PUSH and POP take one additional clock cycle If the stack is pla...

Page 13: ...nternal data SRAM in the ATmega161 are all accessible through all these addressing modes See the next section for a detailed description of the different addressing modes Program and Data Addressing Modes The ATmega161 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory Flash and data memory SRAM register file and I O memory This section descr...

Page 14: ...and address is contained in six bits of the instruction word n is the destination or source register address Data Direct Figure 12 Direct Data Addressing A 16 bit data address is contained in the 16 LSBs of a two word instruction Rd Rr spec ify the destination or source register 0 63 0 5 n OP 15 P I O MEMORY OP Rr Rd 16 31 15 0 16 LSBs 0000 FFFF 20 19 Data Space ...

Page 15: ...e 14 Data Indirect Addressing Operand address is the contents of the X Y or Z register Data Indirect with Pre decrement Figure 15 Data Indirect Addressing with Pre decrement The X Y or Z register is decremented before the operation Operand address is the decremented contents of the X Y or Z register Data Space 0000 FFFF Y OR Z REGISTER OP a n 0 0 5 6 10 15 15 Data Space 0000 FFFF X Y OR Z REGISTER...

Page 16: ... Addressing Using the LPM Instruction Figure 17 Code Memory Constant Addressing Constant byte address is specified by the Z register contents The 15 MSBs select word address 0 8K the LSB selects low byte if cleared LSB 0 or high byte if set LSB 1 Indirect Program Addressing IJMP and ICALL Figure 18 Indirect Program Memory Addressing Data Space 0000 FFFF X Y OR Z REGISTER 0 15 1 1FFF 000 PROGRAM ME...

Page 17: ...tion Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access The AVR CPU is driven by the System Clock Ø directly generated from the external clock crystal for the chip No internal clock division is used Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast...

Page 18: ... Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 23 Figure 23 On chip Data SRAM Access Cycles System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU ...

Page 19: ...er 30 50 SFIOR Special Function IO Register 2F 4F TCCR1A Timer Counter1 Control Register A 2E 4E TCCR1B Timer Counter1 Control Register B 2D 4D TCNT1H Timer Counter1 High Byte 2C 4C TCNT1L Timer Counter1 Low Byte 2B 4B OCR1AH Timer Counter1 Output Compare RegisterA High Byte 2A 4A OCR1AL Timer Counter1 Output Compare RegisterA Low Byte 29 49 OCR1BH Timer Counter1 Output Compare RegisterB High Byte...

Page 20: ...er Port D 10 30 PIND Input Pins Port D 0F 2F SPDR SPI I O Data Register 0E 2E SPSR SPI Status Register 0D 2D SPCR SPI Control Register 0C 2C UDR0 UART0 I O Data Register 0B 2B UCSR0A UART0 Control and Status Register 0A 2A UCSR0B UART0 Control and Status Register 09 29 UBRR0 UART0 Baud Rate Register 08 28 ACSR Analog Comparator Control and Status Register 07 27 PORTE Data Register Port E 06 26 DDR...

Page 21: ...lobal interrupt enable bit must be set one for the interrupts to be enabled The individual interrupt enable control is then performed in separate control registers If the global interrupt enable bit is cleared zero none of the interrupts are enabled indepen dent of the individual interrupt enable settings The I bit is cleared by hardware after an interrupt has occurred and is set by the RETI instr...

Page 22: ...ion and it is decremented by 2 when an address is pushed onto the Stack with subroutine calls and interrupts The Stack Pointer is incremented by 1 when data is popped from the Stack with the POP instruction and it is incremented by 2 when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI Reset and Interrupt Handling The ATmega161 provides 20 differen...

Page 23: ...le 2 Reset and Interrupt Vectors 1 Vector No Program Address Source Interrupt Definition 1 000 RESET External Pin Power on Reset Brown out Reset and Watchdog Reset 2 002 INT0 External Interrupt Request 0 3 004 INT1 External Interrupt Request 1 4 006 INT2 External Interrupt Request 2 5 008 TIMER2 COMP Timer Counter2 Compare Match 6 00a TIMER2 OVF Timer Counter2 Overflow 7 00c TIMER1 CAPT Timer Coun...

Page 24: ...NT1 IRQ1 Handler 006 jmp EXT_INT2 IRQ2 Handler 008 jmp TIM2_COMP Timer2 Compare Handler 00a jmp TIM2_OVF Timer2 Overflow Handler 00c jmp TIM1_CAPT Timer1 Capture Handler 00e jmp TIM1_COMPA Timer1 CompareA Handler 010 jmp TIM1_COMPB Timer1 CompareB Handler 012 jmp TIM1_OVF Timer1 Overflow Handler 014 jmp TIM0_COMP Timer0 Compare Handler 016 jmp TIM0_OVF Timer0 Overflow Handler 018 jmp SPI_STC SPI T...

Page 25: ...tage During reset all I O registers are then set to their initial values and the program starts execution from address 000 The instruction placed in address 000 must be a JMP relative jump instruction to the reset handling routine If the program never enables an interrupt source the interrupt vectors are not used and regular program code can be placed at these locations The circuit diagram in Figu...

Page 26: ...shold Voltage rising BOD disabled 1 0 1 4 1 8 V BOD enabled 1 7 2 2 2 7 V Power on Reset Threshold Voltage falling 1 BOD disabled 0 4 0 6 0 8 V BOD enabled 1 7 2 2 2 7 V VRST RESET Pin Threshold Voltage 0 85 VCC V VBOT Brown out Reset Threshold Voltage BODLEVEL 1 2 6 2 7 2 8 V BODLEVEL 0 3 8 4 0 4 2 Table 4 Reset Delay Selections 4 CKSEL 2 0 Start up Time VCC 2 7V BODLEVEL Unprogrammed Start up Ti...

Page 27: ...pply voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reach ing the Power on Reset threshold voltage invokes a delay counter which determines the delay for which the device is kept in RESET after VCC rise The time out period of the delay counter can be defined by the user through the CKSEL fuses The eight differ ent selections for the delay period are presented i...

Page 28: ...ation The BOD circuit can be enabled disabled by the fuse BODEN When BODEN is enabled BODEN programmed and VCC decreases to a value below the trigger level the Brown out Reset is immediately activated When VCC increases above the trigger level the Brown out Reset is deactivated after a delay The delay is defined by the user in the same way as the delay of POR signal in Table 4 The trigger level fo...

Page 29: ...ring Operation MCU Status Register MCUSR The MCU Status Register provides information on which reset source caused an MCU reset Bits 7 4 Res Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero Bit 3 WDRF Watchdog Reset Flag This bit is set if a Watchdog reset occurs The bit is cleared by a Power on Reset or by writing a logical 0 to the flag VCC RESET TIME OUT INTER...

Page 30: ...t is cleared zero the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software If one or more interrupt conditions occur when the global interrupt enable bit is cleared zero the corresponding interrupt flag s will be set and remembered until the global interrupt enable bit is set one and will be executed by order of priority Note that external lev...

Page 31: ...it in the Status Register SREG is set one the external pin interrupt is activated The Interrupt Sense Control2 bit ISC02 in the Extended MCU Control Register EMCUCR defines whether the external interrupt is activated on rising or falling edge of the INT2 pin Activity on the pin will cause an inter rupt request even if INT2 is configured as an output The corresponding interrupt of External Interrup...

Page 32: ...et one and the I bit in the Status Register is set one the Timer Counter1 CompareB Match interrupt is enabled The corresponding interrupt at vector 010 is executed if a CompareB match in Timer Counter1 occurs i e when the OCF1B bit is set in the Timer Counter Interrupt Flag Register TIFR Bit 4 TOIE2 Timer Counter2 Overflow Interrupt Enable When the TOIE2 bit is set one and the I bit in the Status ...

Page 33: ...A Output Compare Flag 1A The OCF1A bit is set one when a compare match occurs between the Timer Counter1 and the data in OCR1A Output Compare Register 1A OCF1A is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF1A is cleared by writing a logical 1 to the flag When the I bit in SREG and OCIE1A Timer Counter1 Compare match InterruptA Enable and OCF1A a...

Page 34: ...and the data in OCR0 Output Compare Register 0 OCF0 is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF0 is cleared by writing a logical 1 to the flag When the I bit in SREG and OCIE0 Timer Counter0 Compare match InterruptA Enable and the OCF0 are set one the Timer Counter0 Compare match Interrupt is executed External Interrupts The external interrup...

Page 35: ...nterrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaran teed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to generate an interrupt Bits 1 0 ISC01 ISC00 Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activate...

Page 36: ...l interrupt 2 is activated by the external pin INT2 if the SREG I flag and the corresponding interrupt mask in the GIMSK are set If ISC2 is cleared zero a falling edge on INT2 activates the interrupt If ISC2 is set one a rising edge on INT2 activates the interrupt Edges on INT2 are registered asynchronously Pulses on INT2 wider than 50 ns will generate an interrupt Shorter pulses are not guarantee...

Page 37: ...m Power down mode the edge is remembered until the MCU wakes up If a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU This makes the MCU less sensi tive to noise The changed level is sampled twice by the Watchdog oscillator clock and if the input has the required level during this time the MCU will wake up The period...

Page 38: ...ons IO Register SFIOR Refer to page 39 for a detailed description These Timer Counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection which trig gers the counting Timer Counter Prescalers Figure 30 Prescaler for Timer Counter0 and 1 For Timer Counters 0 and 1 the four prescaled selections are CK 8 CK 64 CK 256 and CK 1024 where CK is ...

Page 39: ...er This allows the user to operate with a predictable prescaler Special Function IO Register SFIOR Bits 7 2 Res Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero Bit 1 PSR2 Prescaler Reset Timer Counter2 When this bit is set one the Timer Counter2 prescaler will be reset The bit will be cleared by hardware after the operation is performed Writing a zero to this bi...

Page 40: ...o 8 bit Timer Counters T C0 and T C2 Figure 32 shows the block diagram for Timer Counter0 Figure 33 shows the block dia gram for Timer Counter2 Figure 32 Timer Counter0 Block Diagram 8 BIT DATA BUS TIMER INT FLAG REGISTER TIFR TIMER COUNTER0 TCNT0 8 BIT COMPARATOR OUTPUT COMPARE REGISTER0 OCR0 TIMER INT MASK REGISTER TIMSK 0 0 0 7 7 7 T C CLK SOURCE UP DOWN T C CLEAR CONTROL LOGIC TOV1 OCF1B OCF1A...

Page 41: ... signal is sampled on the rising edge of the internal CPU clock The 8 bit Timer Counters feature both a high resolution and a high accuracy usage with the lower prescaling opportunities Similarly the high prescaling opportunities make the Timer Counter0 useful for lower speed functions or exact timing functions with infre quent actions Timer Counters 0 and 2 can also be used as 8 bit Pulse Width M...

Page 42: ...termine any output pin action following a com pare match in Timer Counter0 or Timer Counter2 Output pin actions affect pins PB0 OC0 or PB1 OC2 This is an alternative function to an I O port and the corre sponding direction control bit must be set one to control an output pin The control configuration is shown in Table 9 Notes 1 In PWM mode these bits have a different function Refer to Table 12 for...

Page 43: ...ondition provides a Timer Enable Disable function The prescaled modes are scaled directly from the CK oscillator clock for Timer Counter0 and PCK2 for Timer Counter2 If the external pin modes are used for Timer Counter0 transitions on PB0 T0 will clock the counter even if the pin is configured as an output This feature can give the user software control of the counting Table 10 Clock 0 Prescale Se...

Page 44: ... up down mode is selected the Timer Counter and the Output Compare Registers OCR0 or OCR2 form an 8 bit free running glitch free and phase correct PWM with outputs on the PB0 OC0 PWM0 or PB1 OC2 PWM2 pin If the overflow mode is selected the Timer Counter and the Output Compare Registers OCR0 or OCR2 form an 8 bit free running and glitch free PWM operating with twice the speed of the up down counti...

Page 45: ...s prevents the occurrence of odd length PWM pulses glitches in the event of an unsynchronized OCR0 or OCR2 write See Figure 34 and Figure 35 for examples Figure 34 Effects of Unsynchronized OCR Latching in Up Down Mode Table 12 Compare Mode Select in PWM Mode 1 CTCn COMn1 COMn0 Effect on Compare Pin Frequency 0 0 0 Not connected 0 0 1 Not connected 0 1 0 Cleared on compare match up counting Set on...

Page 46: ... valid for OCRn FF In up down PWM mode the Timer Overflow Flag TOV0 or TOV2 is set when the counter advances from 00 In overflow PWM mode the Timer Overflow Flag is set as in normal Timer Counter mode Timer Overflow Interrupt0 and 2 operate exactly as in normal Timer Counter mode i e they are executed when TOV0 or TOV2 are set pro vided that Timer Overflow Interrupt and global interrupts are enabl...

Page 47: ...e its update busy flag is set one the updated value might get corrupted and cause an unintentional inter rupt to occur The mechanisms for reading TCNT2 OCR2 and TCCR2 are different When reading TCNT2 the actual timer value is read When reading OCR2 or TCCR2 the value in the temporary storage register is read Asynchronous Operation of Timer Counter2 When Timer Counter2 operates asynchronously some ...

Page 48: ... to zero 3 Enter Power save mode When asynchronous operation is selected the 32 kHz oscillator for Timer Counter2 is always running except in Power down mode After a Power up Reset or wake up from power down the user should be aware of the fact that this oscillator might take as long as one second to stabilize The user is advised to wait for at least one second before using Timer Counter2 after po...

Page 49: ...escaling opportunities Similarly the high prescaling opportunities make the Timer Counter1 useful for lower speed functions or exact timing functions with infrequent actions The Timer Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B OCR1A and OCR1B as the data sources to be compared to the Timer Counter1 contents The Output Compare functions include option...

Page 50: ... actual trigger condition for the capture event is monitored over four samples and all four must be equal to activate the capture flag Timer Counter1 Control Register A TCCR1A Bits 7 6 COM1A1 COM1A0 Compare Output Mode1A Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer Counter1 Any output pin actions affect pin OC1A Output CompareA ...

Page 51: ...ompare match output pin PE2 according to the values already set in COM1B1 and COM1B0 If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B the new settings will not take effect until the next compare match or forced compare match occurs The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer The automatic action programmed i...

Page 52: ... Counter1 on Compare Match When the CTC1 control bit is set one the Timer Counter1 is reset to 0000 in the clock cycle after a compareA match If the CTC1 control bit is cleared Timer Counter1 contin ues counting and is unaffected by a compare match When a prescaling of 1 is used and the compareA register is set to C the timer will count as follows if CTC1 is set C 1 C 0 1 When the prescaler is set...

Page 53: ...the byte data in the TEMP register and all 16 bits are written to the TCNT1 Timer Counter1 register simultaneously Consequently the high byte TCNT1H must be accessed first for a full 16 bit register write operation TCNT1 Timer Counter1 Read When the CPU reads the low byte TCNT1L the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register W...

Page 54: ...ogram and interrupt routines perform access to registers using TEMP interrupts must be dis abled during access from the main program and interrupt routines Timer Counter1 Input Capture Register ICR1H AND ICR1L The input capture register is a 16 bit read only register When the rising or falling edge according to the input capture edge setting ICES1 of the signal at the input capture pin ICP is dete...

Page 55: ...mer Counter1 and the Output Com pare Register1A OCR1A and the Output Compare Register1B OCR1B form a dual 8 9 or 10 bit free running and glitch free PWM with outputs on the PD5 OC1A and PE2 OC1B pins As shown in Table 17 the PWM operates at either 8 9 or 10 bit resolution Note the unused bits in OCR1A OCR1B and TCNT1 will automatically be written to zero by hard ware i e bits 9 to 15 will be set t...

Page 56: ...rflow Mode1 Note 1 Note X A or B During the time between the write and the latch operation a read from OCR1A or OCR1B will read the contents of the temporary location This means that the most recently written value always will read out of OCR1A B When the OCR1X contains 0000 or TOP and the up down PWM mode is selected the output OC1A OC1B is updated to low or high on the next compare match accordi...

Page 57: ...he counter advances from 0000 In overflow PWM mode the Timer Overflow flag is set as in nor mal Timer Counter mode Timer Overflow Interrupt1 operates exactly as in normal Timer Counter mode i e it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled This also applies to the Timer Output Compare1 flags and interrupts Table 19 PWM Outputs OCR1X 0000 ...

Page 58: ...ollowed when the Watchdog is disabled Refer to the description of the Watchdog Timer Control Register for details Figure 40 Watchdog Timer Watchdog Timer Control Register WDTCR Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATmega161 and will always read as zero Bit 4 WDTOE Watchdog Turn off Enable This bit must be set one when the WDE bit is cleared Otherwise the watchdog will not...

Page 59: ... in the Elec trical Characteristics section The WDR Watchdog Reset instruction should always be executed before the Watchdog Timer is enabled This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings If the Watchdog Timer is enabled without reset the Watchdog Timer may not start counting from zero To avoid unintentional MCU Reset the Watchdog Timer should b...

Page 60: ... When the EEPROM is written the CPU is halted for two clock cycles before the next instruction is executed When the EEPROM is read the CPU is halted for four clock cycles before the next instruction is executed EEPROM Address Register EEARH and EEARL Bits 15 9 Res Reserved Bits These bits are reserved bits in the ATmega161 and will always read as zero Bits 8 0 EEAR8 0 EEPROM Address The EEPROM Add...

Page 61: ...R optional 3 Write new EEPROM data to EEDR optional 4 Write a logical 1 to the EEMWE bit in EECR to be able to write a logical 1 to the EEMWE bit the EEWE bit must be written to zero in the same cycle 5 Within four clock cycles after setting EEMWE write a logical 1 to EEWE Caution An interrupt between step 4 and step 5 will make the write cycle fail since the EEPROM Master Write Enable will time o...

Page 62: ...age for executing instructions is too low EEPROM data corruption can easily be avoided by following these design recommen dations one is sufficient 1 Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating voltage matches the detection level If not an external low VCC Reset Protection circui...

Page 63: ...AVR devices The ATmega161 SPI features include the following Full duplex 3 wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake up from Idle Mode Slave Mode Only Double speed CK 2 Master SPI Mode Figure 41 SPI Block Diagram SPI2X SPI2X DIVIDER 2 4 8 16 32 64...

Page 64: ...s single buffered in the transmit direction and double buffered in the receive direction This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed When receiving data however a received byte must be read from the SPI Data Register before the next byte has been completely shifted in Otherwise the first byte is lost When the SPI is ...

Page 65: ...it must be set by the user to re enable SPI master mode When the SPI is configured as a slave the SS pin is always input When SS is held low the SPI is activated and MISO becomes an output if configured so by the user All other pins are inputs When SS is driven high all pins are inputs and the SPI is passive which means that it will not receive incoming data Note that the SPI logic will be reset o...

Page 66: ... set MSTR to re enable SPI master mode Bit 3 CPOL Clock Polarity When this bit is set one SCK is high when idle When CPOL is cleared zero SCK is low when idle Refer to Figure 43 and Figure 44 for additional information Bit 2 CPHA Clock Phase Refer to Figure 43 or Figure 44 for the functionality of this bit Bits 1 0 SPR1 SPR0 SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the ...

Page 67: ...es Reserved Bits These bits are reserved bits in the ATmega161 and will always read as zero Bit 0 SPI2X Double SPI Speed Bit When this bit is set one the SPI speed SCK frequency will be doubled when the SPI is in master mode see Table 23 This means that the maximum SCK period will be two CPU clock periods When the SPI is configured as slave the SPI is only guaranteed to work at fcl 4 The SPI inter...

Page 68: ...identical and the functionality is described in general for the two UARTs Figure 45 UART Transmitter Data transmission is initiated by writing the data to be transmitted to the UART I O Data Register UDRn Data is transferred from UDRn to the Transmit shift register when A new character has been written to UDRn after the stop bit from the previous character has been shifted out The shift register i...

Page 69: ...ansfer operation to the shift register the start bit is shifted out on the TXDn pin Then follows the data LSB first When the stop bit has been shifted out the shift register is loaded if any new data has been written to the UDRn during the transmission During loading UDREn is set If there is no new data in the UDRn register to send when the stop bit is shifted out the UDREn flag will remain set un...

Page 70: ...ver a valid start bit is detected sampling of the data bits following the start bit is performed These bits are also sampled at samples 8 9 and 10 The logical value found in at least two of the three samples is taken as the bit value All bits are shifted into the transmitter shift register as they are sampled Sampling of an incoming character is shown in Figure 47 Note that the description above i...

Page 71: ...ud rate is high or CPU load is high When the RXEN bit in the UCSRnB register is cleared zero the receiver is disabled This means that the PD0 pin can be used as a general I O pin When RXEN is set the UART receiver will be connected to PD0 UART0 or PB2 UART1 which is forced to be an input pin regardless of the setting of the DDD0 in DDRD UART0 or DDB2 bit in DDRB UART1 When PD0 UART0 or PB2 UART1 i...

Page 72: ...iving MCU will also generate a framing error FEn in UCSRnA set since the stop bit is zero The other slave MCUs which still have the MPCMn bit set will ignore the data byte In this case the UDRn register and the RXCn FEn or flags will not be affected 5 After the last byte has been transferred the process repeats from step 2 UART Control UART0 I O Data Register UDR0 UART1 I O Data Register UDR1 The ...

Page 73: ...nsmit shift register Setting of this bit indicates that the transmitter is ready to receive a new charac ter for transmission When the UDRIEn bit in UCSRnB is set the UART Transmit Complete interrupt will be executed as long as UDREn is set and the global interrupt enable bit in SREG is set UDREn is cleared by writing UDRn When interrupt driven data transmittal is used the UART Data Register Empty...

Page 74: ... Receiver Enable This bit enables the UART receiver when set one When the receiver is disabled the TXCn ORn and FEn status flags cannot become set If these flags are set turning off RXEN does not cause them to be cleared Bit 3 TXEN0 TXEN1 Transmitter Enable This bit enables the UART transmitter when set one When disabling the transmitter while transmitting a character the transmitter is not disabl...

Page 75: ... UBR 3 0 0 UBR 3 7 8 UBR 4 6 3 38400 UBR 1 22 9 UBR 2 0 0 UBR 2 7 8 UBR 3 0 0 57600 UBR 0 7 8 UBR 1 0 0 UBR 1 7 8 UBR 2 12 5 76800 UBR 0 22 9 UBR 1 33 3 UBR 1 22 9 UBR 1 0 0 115200 UBR 0 84 3 UBR 0 0 0 UBR 0 7 8 UBR 0 25 0 Baud Rate 3 2768 MHz Error 3 6864 MHz Error 4 MHz Error 4 608 MHz Error 2400 UBR 84 0 4 UBR 95 0 0 UBR 103 0 2 UBR 119 0 0 4800 UBR 42 0 8 UBR 47 0 0 UBR 51 0 2 UBR 59 0 0 9600 ...

Page 76: ...e four most significant bits of the UART0 baud register UART0 Baud Rate Register Low Byte UBRR0 UART1 Baud Rate Register Low Byte UBRR1 UBRRn stores the eight least significant bits of the UART baud rate register Bit 7 6 5 4 3 2 1 0 20 40 MSB1 LSB1 MSB0 LSB0 UBRRHI Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 09 29 MSB LSB UBRR0 Read Write R W R W R ...

Page 77: ...These bits are also sampled at samples 4 5 and 6 The logical value found in at least two of the three samples is taken as the bit value All bits are shifted into the transmitter shift register as they are sampled Sampling of an incoming character is shown in Figure 48 Figure 48 Sampling Received Data when the Transmission Speed is Doubled The Baud Rate Generator in Double UART Speed Mode Note that...

Page 78: ...BR 20 UBR 13 UBR 10 UBR 6 UBR 4 UBR 3 UBR 1 UBR 0 0 2 0 4 0 8 1 6 1 6 1 6 3 1 1 6 6 2 12 5 12 5 12 5 UBR 191 UBR 95 UBR 47 UBR 31 UBR 23 UBR 15 UBR 11 UBR 7 UBR 5 UBR 3 UBR 1 UBR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBR 207 UBR 103 UBR 51 UBR 34 UBR 25 UBR 16 UBR 12 UBR 8 UBR 6 UBR 3 UBR 1 UBR 0 UBR 0 0 2 0 2 0 2 0 8 0 2 2 1 0 2 3 7 7 5 7 8 7 8 7 8 84 3 Baud Rate 7 3728 MHz Error 8 00...

Page 79: ...tus Register ACSR Bit 7 ACD Analog Comparator Disable When this bit is set one the power to the Analog Comparator is switched off This bit can be set at any time to turn off the Analog Comparator This will reduce power con sumption in active and idle mode When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur whe...

Page 80: ...s given To make the comparator trigger the Timer Counter1 Input Capture Interrupt the TICIE1 bit in the Timer Interrupt Mask Register TIMSK must be set one Bits 1 0 ACIS1 ACIS0 Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator Interrupt The different settings are shown in Table 26 Note 1 When changing the ACIS1 ACIS0 bits the Analog ...

Page 81: ...sed The maximum start up time is TBD To save power the reference is on during the following situations only 1 When BOD is enabled by programming the BODEN fuse 2 When the bandgap reference is connected to the Analog Comparator by setting the AINBG bit in ACSR Thus when BOD is not enabled after setting the AINBG bit the user must always allow the reference to start up before the output from the Ana...

Page 82: ...ed Bits 6 4 EMCUCR SRL2 SRL1 SRL0 Wait State Page Limit It is possible to configure different wait states for different external memory addresses The external memory address space can be divided into two pages with different wait state bits The SRL2 SRL1 and SRL0 bits select the split of the pages see Table 28 and Figure 50 As defaults the SRL2 SRL1 and SRL0 bits are set to zero and the entire ext...

Page 83: ...t States 0 0 No wait states 0 1 Wait one cycle during read write strobe 1 0 Wait two cycles during read write strobe 1 1 Wait two cycles during read write and wait one cycle before driving out new address Table 28 Page Limits with Different Settings of SRL2 0 SRL2 SRL1 SRL0 Page Limits 0 0 0 Lower page N A Upper page 0460 FFFF 0 0 1 Lower page 0460 1FFF Upper page 2000 FFFF 0 1 0 Lower page 0460 4...

Page 84: ...ly present if the next instruction accesses the RAM internal or external The Data and Address will only change in T4 if ALE is present the next instruction accesses the RAM 0000 Data Memory 0460 External Memory 0 63K x 8 FFFF Internal memory SRL 2 0 SRW11 SRW10 SRW01 SRW00 Lower page Upper page System Clock Ø ALE WR RD Data Address 7 0 Data Address 7 0 Address 15 8 Address Address Address T1 T2 T3...

Page 85: ...accesses the RAM Figure 54 External Data Memory Cycles with SRWn1 1 and SRWn0 1 1 Note 1 SRWn1 SRW11 upper page or SRW01 lower page SRWn0 SRW10 upper page or SRW00 lower page The ALE pulse in period T7 is only present if the next instruction accesses the RAM internal or external The Data and Address will only change in T7 if ALE is present the next instruction accesses the RAM System Clock Ø ALE W...

Page 86: ... above the internal SRAM boundary is not mapped into the internal SRAM as in AVR parts do not have an external memory interface When ALE goes from high to low there is a valid address on Port A ALE is low during a data transfer RD and WR are active when accessing the external memory only When the external memory interface is enabled the ALE signal may have short pulses when accessing the internal ...

Page 87: ...stors When Port A is set to the alternate function by the SRE External SRAM Enable bit in the MCUCR MCU Control Register the alternate settings override the Data Direction Register Port A Data Register PORTA Port A Data Direction Register DDRA Port A Input Pins Address PINA The Port A Input Pins address PINA is not a register this address enables access to the physical value on each Port A pin Whe...

Page 88: ... that all port pins are synchronized The synchronization latch is however not shown in the figure Figure 56 Port A Schematic Diagrams Pins PA0 PA7 Table 29 DDAn Effects on Port A Pins 1 DDAn PORTAn I O Pull up Comment 0 0 Input No Tri state high Z 0 1 Input Yes PAn will source current if ext pulled low 1 0 Output No Push pull Zero Output 1 1 Output No Push pull One Output ...

Page 89: ...ess PINB is not a register this address enables access to the physical value on each Port B pin When reading PORTB the Port B Data Latch is read and when reading PINB the logical values present on the pins are read Table 30 Port B Pin Alternate Functions 1 Port Pin Alternate Functions PB0 OC0 Timer Counter0 Compare Match Output T0 Timer Counter0 External Counter Input PB1 OC2 Timer Counter2 Compar...

Page 90: ...a slave the data direction of this pin is controlled by DDB6 When the pin is forced to be an input the pull up can still be controlled by the PORTB6 bit See the description of the SPI port for further details MOSI Port B Bit 5 MOSI SPI Master data output slave data input for SPI channel When the SPI is enabled as a slave this pin is configured as an input regardless of the setting of DDB5 When the...

Page 91: ...serve as an external output when the Timer Counter2 compare matches The PB1 pin has to be configured as an output DDB1 set one to serve this function See 8 bit Timer Counters T C0 and T C2 on page 40 for further details The OC2 pin is also the output pin for the PWM mode timer function OC0 T0 Port B Bit 0 T0 Timer Counter0 counter source See 8 bit Timer Counters T C0 and T C2 on page 40 further de...

Page 92: ...onized The synchronization latches are however not shown in the figures Figure 57 Port B Schematic Diagram Pins PB0 and PB1 PBn DDBn PORTBn COMP MATCH x COMx0 COMx1 WP WD RL RP RD WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB FOCx PWMx n 0 1 x 0 2 CSn2 CSn1 CSn0 ...

Page 93: ... WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB UART1 RECEIVE DATA UART1 RECEIVE ENABLE DDB2 PORTB2 RL RP AIN0 ANALOG COMPARATOR POSITIVE INPUT AIN0 DATA BUS D D Q Q RESET RESET C C WD WP RD RP RL MOS PULL UP PB3 R R WP WD RL RP RD TXD1 TXEN1 WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB UART1 TRANSMIT DATA UART1 TRANSMIT ENABLE DDB3 PORTB3 TXEN1 TXD1 AIN1 AIN1 ANALOG COMP...

Page 94: ...S MSTR SPE WP WD RL RP RD MSTR SPE WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE DDB4 PORTB4 RL RP DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PB5 R R WP WD RL RP RD SPE MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT DDB5 PORTB5 SPE MSTR SPI MASTER OUT SPI SLAVE IN RL RP ...

Page 95: ... RD SPE MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT DDB6 PORTB6 SPE MSTR SPI SLAVE OUT SPI MASTER IN RL RP DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PB7 R R WP WD RL RP RD SPE MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT DDB7 PORTB7 SPE MSTR SPI ClLOCK OUT SPI CLOCK IN RL RP ...

Page 96: ...ort C Input Pins address PINC is not a register this address enables access to the physical value on each Port C pin When reading PORTC the Port C Data Latch is read and when reading PINC the logical values present on the pins are read Port C as General Digital I O All eight pins in Port C have equal functionality when used as digital I O pins PCn general I O pin The DDCn bit in the DDRC register ...

Page 97: ...nization latch is however not shown in the figure Figure 64 Port C Schematic Diagram Pins PC0 PC7 Table 32 DDCn Effects on Port C Pins 1 DDCn PORTCn I O Pull up Comment 0 0 Input No Tri state high Z 0 1 Input Yes PCn will source current if ext pulled low 1 0 Output No Push pull Zero Output 1 1 Output No Push pull One Output ...

Page 98: ... values present on the pins are read Port D as General Digital I O PDn general I O pin The DDDn bit in the DDRD register selects the direction of this pin If DDDn is set one PDn is configured as an output pin If DDDn is cleared zero PDn is configured as an input pin If PORTDn is set one when configured as an input pin the MOS pull up resistor is activated To switch the pull up resistor off the POR...

Page 99: ...isconnected from the port In this mode a crystal oscillator is connected to the pins and the pins cannot be used as I O pins INT1 Port D Bit 3 INT1 External Interrupt source 1 The PD3 pin can serve as an external interrupt source to the MCU See MCU Control Register MCUCR on page 34 for further details INT0 Port D Bit 2 INT0 External Interrupt source 0 The PD2 pin can serve as an external interrupt...

Page 100: ...ATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PD0 RXD0 RXEN0 WP WD RL RP RD RXD0 RXEN0 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART0 RECEIVE DATA UART0 RECEIVE ENABLE DDD0 PORTD0 RL RP DATA BUS D D Q Q RESET RESET C C WD WP RD RP RL MOS PULL UP PD1 R R WP WD RL RP RD TXD0 TXEN0 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART0 TRANSMIT DATA UART...

Page 101: ...agram Pin PD4 WP WD RL RP RD n m WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 2 3 0 1 DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PD4 R R WP WD RL RP RD AS2 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD ASYNCH SELECT T C2 DDD4 PORTD4 RL RP AS2 T C2 OSC AMP INPUT ...

Page 102: ...t D Schematic Diagram Pin PD6 COMP MATCH 1A FOC1A PWM10 PWM11 WP WD RL RP RD AS2 WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD ASYNCH SELECT T C2 WP WD RL RP RD WE SRE WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD WRITE ENABLE EXTERNAL SRAM ENABLE ...

Page 103: ...103 ATmega161 L 1228B 09 01 Figure 71 Port D Schematic Diagram Pin PD7 WP WD RL RP RD RE SRE WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD READ ENABLE EXTERNAL SRAM ENABLE ...

Page 104: ...ata Latch is read and when reading PINE the logical values present on the pins are read Port E as General Digital I O PEn general I O pin The DDEn bit in the DDRE register selects the direction of this pin If DDEn is set one PEn is configured as an output pin If DDEn is cleared zero PEn is configured as an input pin If PORTEn is set one when configured as an input pin the MOS pull up resistor is a...

Page 105: ...serves as the Dress Latch Enable Note that enabling of External Memory will override both the direction and port value See Interface to External Memory on page 82 for a detailed description ICP INT2 Port E Bit 0 ICP input capture pin The PE0 pin can serve as the input capture source for Timer Counter 1 See page 54 for a detailed description INT2 External Interrupt source 2 The PE0 pin can serve as...

Page 106: ...PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE COMPARATOR IC ENABLE COMPARATOR OUTPUT DDE0 PORTE0 NOISE CANCELER EDGE SELECT ICF1 ICNC1 ICES1 0 1 ACIC ACO RL RP D Q C R PORTE0 ISC2 1 INT2 SW CLEAR HW CLEAR DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PE1 R R WP WD RL RP RD SRE WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE DDE1 PORTE1 RL RP SRE ALE XRAM ENABL...

Page 107: ...Tmega161 L 1228B 09 01 Figure 74 Port E Schematic Diagram Pin PE2 PE2 DDE2 PORTE2 COMP MATCH 1B COM1B0 COM1B1 WP WD RL RP RD WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE FOC1B PWM10 PWM11 ...

Page 108: ...ce to input or output program code and write program that code into the Flash memory or read the code from the program memory The program Flash memory is divided into pages that each contain 128 bytes The Boot Loader Flash section occupies eight pages from 1E00 to 1FFF by 16 bit words The Store Program Memory SPM instruction can access the entire Flash but it can only be executed from the Boot Loa...

Page 109: ...e Boot Reset Fuse is programmed the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface The BOOTRST fuse can also be locked by program ming LB1 When LB1 is programmed it is not possible to change the BOOTRST fuse unless a Chip Erase command is performed first Table 37 Boot Lock Bit0 Protection Modes Applicati...

Page 110: ... to be changed the other parts must be stored for example in the temporary page buffer before the erase and then be rewritten The temporary page buffer can be accessed in a random sequence The CPU is halted both during page erase and during page write and the SPMEN bit in the SPMCR register will be auto cleared For future compatibility however it is recom mended that the user software verify that ...

Page 111: ...nly operation that does not use the Z pointer is setting the Boot Loader Lock bits The content of the Z pointer is ignored and will have no effect on the operation Note that the page erase and page write operation are addressed independently There fore it is of major importance that the Boot Loader software addresses the same page in both the page erase and page write operations The LPM instructio...

Page 112: ...during the entire page write operation Bit 1 PGERS Page Erase If this bit is set at the same time as SPMEN the next SPM instruction within four clock cycles executes a page erase The page address is taken from the high part of the Z pointer The data in R1 and R0 are ignored The PGERS bit will auto clear upon comple tion of a page erase or if no SPM instruction is executed within four clock cycles ...

Page 113: ... within three four CPU cycles When BLBSET and SPMEN are cleared LPM will work as described in Constant Addressing Using the LPM Instruction on page 16 and in the Instruction Set manual The algorithm for reading the Fuse bits is similar to the one described above for reading the Lock bits But when reading the Fuse bits load 0000 in the Z pointer When an LPM instruction is executed within three cycl...

Page 114: ...f the Flash and EEPROM is disabled in parallel and serial programming modes The Fuse bits are locked in both serial and parallel programming modes 1 3 0 0 Further programming and verification of the Flash and EEPROM is disabled in parallel and serial programming modes The Fuse bits are locked in both serial and parallel programming modes 1 BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM LPM ac...

Page 115: ... pro grammed This device supports a high voltage 12V parallel programming mode and a low voltage serial programming mode The 12V is used for programming enable only and no current of significance is drawn by this pin The serial programming mode pro vides a convenient way to download the program and data into the ATmega161 inside the user s system The program memory array on the ATmega161 is organi...

Page 116: ... Mapping Signal Name in Programming Mode Pin Name I O Function RDY BSY PD1 O 0 Device is busy programming 1 Device is ready for new command OE PD2 I Output Enable Active low WR PD3 I Write Pulse Active low BS1 PD4 I Byte Select 1 0 selects low byte 1 selects high byte XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory Page Load BS2 PA0 I Byte Select 2 Always low DAT...

Page 117: ...g the Flash The Flash is organized as 128 pages of 128 bytes each When programming the Flash the program data is latched into a page buffer This allows one page of program data to be programmed simultaneously The following procedure describes how to program the entire Flash memory A Load Command Write Flash 1 Set XA1 XA0 to 10 This enables command loading 2 Set BS1 to 0 3 Set DATA to 0001 0000 Thi...

Page 118: ...gh F 64 times to fill the page buffer To address a page in the Flash seven bits are needed 128 pages The five most sig nificant bits are read from address high byte as described in section H below The two least significant page address bits however are the two most significant bits bit7 and bit6 of the latest loaded address low byte as described in section B H Load Address High byte 1 Set XA1 XA0 ...

Page 119: ...s on command address and data loading 1 A Load Command 0001 0001 2 H Load Address High Byte 00 01 3 B Load Address Low Byte 00 FF 4 E Load Data Low Byte 00 FF L Write Data Low Byte 1 Set BS to 0 This selects low data 2 Give WR a negative pulse This starts programming of the data byte RDY BSY goes low 10 ADDR LOW ADDR HIGH DATA LOW DATA XA1 XA2 BS1 XTAL1 RDY BSY RESET WR OE 12V BS2 PAGEL DATA HIGH ...

Page 120: ...the EEPROM Waveforms Reading the Flash The algorithm for reading the Flash memory is as follows refer to Programming the Flash on page 117 for details on command and address loading 1 A Load Command 0000 0010 2 H Load Address High Byte 00 1F 3 B Load Address Low Byte 00 FF 4 Set OE to 0 and BS1 to 0 The Flash word low byte can now be read at DATA 5 Set BS to 1 The Flash word high byte can now be r...

Page 121: ... Bit01 Bit 1 Lock Bit2 Bit 0 Lock Bit1 Bits 7 6 1 These bits are reserved and should be left unprogrammed 1 3 L Write Data Low Byte The Lock bits can only be cleared by executing Chip Erase Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows refer to Programming the Flash on page 117 for details on command loading 1 A Load Command 0000 0100 2 Set OE to 0 a...

Page 122: ...e can now be read at DATA 3 Set OE to 1 Parallel Programming Characteristics Figure 80 Parallel Programming Timing Data Control DATA XA0 1 BS1 DATA Write Read XTAL1 tXHXL tWLWH tDVXH tXLOL tOLDV tXLDX tPLWL tWLRH WR RDY BSY OE PAGEL tPHPL tPLBX tBVXH tXLWL tRHBX tOHDZ tBVWL WLRL ...

Page 123: ...ROM memory Either an external system clock is supplied at pin XTAL1 or a crystal needs to be con nected across pins XTAL1 and XTAL2 The minimum low and high periods for the serial clock SCK input are defined as follows Low 2 XTAL1 clock cycles High 2 XTAL1 clock cycles Table 45 Parallel Programming Characteristics TA 25 C 10 VCC 5V 10 1 2 3 Symbol Parameter Min Typ Max Units VPP Programming Enable...

Page 124: ...time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address If polling is not used the user must wait at least tWD_FLASH before issu ing the next page please refer to Table 46 Accessing the serial programming interface before the Flash ...

Page 125: ...ld keep the following in mind As a chip erased device contains FF in all locations programming of addresses that are meant to contain FF can be skipped This does not apply if the EEPROM is reprogrammed without chip erasing the device In this case data polling cannot be used for the value FF and the user will have to wait at least tWD_EEPROM before programming the next byte See Table 46 for tWD_EEP...

Page 126: ... b Load Program Memory Page 0100 H000 xxxx xxxx xxbb bbbb iiii iiii Write H high or low data i to program memory page at word address b Write Program Memory Page 0100 1100 xxxa aaaa bbxx xxxx iiii iiii Write program memory page at address a b Read EEPROM Memory 1010 0000 xxxx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a b Write EEPROM Memory 1100 0000 xxxx xxxa bbbb bbbb ii...

Page 127: ... Parameter Min Typ Max Units 1 tCLCL Oscillator Frequency VCC 2 7 5 5V 0 4 MHz VCC 4 0 5 5V 0 8 MHz tCLCL Oscillator Period VCC 2 7 5 5V 250 ns VCC 4 0 5 5V 125 ns tSHSL SCK Pulse Width High 2 tCLCL ns tSLSH SCK Pulse Width Low 2 tCLCL ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid 10 16 32 ns MOSI MISO SCK tOVSH tSHSL tSLSH tSHOX tSL...

Page 128: ...s 200 0 mA DC Characteristics TA 40 C to 85 C VCC 2 7V to 5 5V unless otherwise noted 1 2 3 4 5 Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL1 0 5 0 3 VCC 1 V VIL1 Input Low Voltage XTAL1 0 5 0 2 VCC 1 V VIH Input High Voltage Except XTAL1 RESET 0 6 VCC 2 VCC 0 5 V VIH1 Input High Voltage XTAL1 0 8 VCC 2 VCC 0 5 V VIH2 Input High Voltage RESET 0 9 VCC 2 VCC 0 5 V V...

Page 129: ... Although each I O port can source more than the test conditions 3 mA at VCC 5V 1 5 mA at VCC 3V under steady state conditions non transient the following must be observed 1 The sum of all IOH for all ports should not exceed 200 mA 2 The sum of all IOH for ports B0 B7 D0 D7 and XTAL2 should not exceed 100 mA 3 The sum of all IOH for ports A0 A7 ALE OC1B and C0 C7 should not exceed 100 mA If IOH ex...

Page 130: ... duty cycle influences the timing for the external data memory Table 50 External Clock Drive 1 Symbol Parameter VCC 2 7V to 5 5V VCC 4 0V to 5 5V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 4 0 8 MHz tCLCL Clock Period 250 125 ns tCHCX High Time 100 50 ns tCLCX Low Time 100 50 ns tCLCH Rise Time 1 6 0 5 µs tCHCL Fall Time 1 6 0 5 µs VIL1 VIH1 ...

Page 131: ...alid to RD Low 95 1 0tCLCL 30 ns 6 tAVWL Address Valid to WR Low 95 1 0tCLCL 30 ns 7 tLLWL ALE Low to WR Low 42 5 145 0 5tCLCL 20 2 0 5tCLCL 20 2 ns 8 tLLRL ALE Low to RD Low 42 5 145 0 5tCLCL 20 2 0 5tCLCL 20 2 ns 9 tDVRH Data Setup to RD High 60 60 ns 10 tRLDV Read Low to Data Valid 65 65 ns 11 tRHDX Data Hold After RD High 0 0 ns 12 tRLRH RD Pulse Width 105 1 0tCLCL 20 ns 13 tDVWL Data Setup to...

Page 132: ... High 152 5 1 5tCLCL 35 ns 15 tDVWH Data Valid to WR High 345 3 0tCLCL 30 ns 16 tWLWH WR Pulse Width 355 3 0tCLCL 20 ns Table 55 External Data Memory Characteristics 2 7 5 5 Volts No Wait State Symbol Parameter 4 MHz Oscillator Variable Oscillator Unit Min Max Min Max 0 1 tCLCL Oscillator Frequency 0 0 4 0 MHz 1 tLHLL ALE Pulse Width 195 tCLCL 55 ns 2 tAVLL Address Valid A to ALE Low 60 0 5tCLCL 6...

Page 133: ...cy 0 0 4 0 MHz 10 tRLDV Read Low to Data Valid 335 2 0tCLCL 165 ns 12 tRLRH RD Pulse Width 480 2 0tCLCL 20 ns 15 tDVWH Data Valid to WR High 460 2 0tCLCL 40 ns 16 tWLWH WR Pulse Width 480 2 0tCLCL 20 ns Table 57 External Data Memory Characteristics 2 7 5 5 Volts SRWn1 1 SRWn0 0 Symbol Parameter 4 MHz Oscillator Variable Oscillator Unit Min Max Min Max 0 1 tCLCL Oscillator Frequency 0 0 4 0 MHz 10 ...

Page 134: ...0 Address Data XX Write Data Address 7 0 Address Data XX System Clock Ø T1 T2 T3 T4 1 4 2 7 6 3a 3b 5 8 12 16 13 15 9 10 11 14 Prev addr XX Prev data XX Prev data ALE WR RD Address 15 8 Address XX XX Read Data Address 7 0 Address Data XX Write Data Address 7 0 Address Data XX T1 T2 T3 T5 1 4 2 7 6 3a 3b 5 8 12 16 13 15 9 10 11 14 Prev addr XX Prev data XX Prev data System Clock Ø T4 ...

Page 135: ...E is present the next instruction accesses the RAM ALE WR RD Address 15 8 Address XX XX Read Data Address 7 0 Address Data XX Write Data Address 7 0 Address Data XX T1 T2 T3 T6 1 4 2 7 6 3a 3b 5 8 12 16 13 15 9 10 11 14 Prev addr XX Prev data XX Prev data System Clock Ø T4 T5 ALE WR RD Address 15 8 Address XX XX Read Data Address 7 0 Address Data XX Write Data Address 7 0 Address Data XX T1 T2 T3 ...

Page 136: ... 89 Analog Comparator Offset Voltage vs Common Mode Voltage 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE VCC 5V COMMON MODE VOLTAGE V OFFSET VOLTAGE mV TA 25 C TA 85 C 0 2 4 6 8 10 0 0 5 1 1 5 2 2 5 3 ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE VCC 2 7V COMMON MODE VOLTAGE V OFFSET VOLTAGE mV TA 25 C TA 85 C ...

Page 137: ...source capabilities of I O ports are measured on one pin at a time 60 50 40 30 20 10 0 10 0 0 5 1 5 1 2 2 5 3 5 3 4 4 5 5 6 6 5 7 5 5 ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC 6V TA 25 C I ACLK nA VIN V 0 200 400 600 800 1000 1200 1400 1600 2 2 5 3 3 5 4 4 5 5 5 5 6 WATCHDOG OSCILLATOR FREQUENCY vs VCC VCC V F RC kHz TA 25 C TA 85 C ...

Page 138: ...ull up Resistor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 5V TA 25 C TA 85 C I OP µA VOP V 0 5 10 15 20 25 30 0 0 5 1 1 5 2 2 5 3 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE VCC 2 7V TA 25 C TA 85 C I OP µA VOP V ...

Page 139: ...Pin Source Current vs Output Voltage 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 I O PIN SINK CURRENT vs OUTPUT VOLTAGE VCC 5V TA 25 C TA 85 C I OL mA VOL V 0 2 4 6 8 10 12 14 16 18 20 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE VCC 5V TA 25 C TA 85 C I OH mA VOH V ...

Page 140: ...ge Figure 97 I O Pin Source Current vs Output Voltage 0 5 10 15 20 25 0 0 5 1 1 5 2 I O PIN SINK CURRENT vs OUTPUT VOLTAGE VCC 2 7V TA 25 C TA 85 C I OL mA VOL V 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE VCC 2 7V TA 25 C TA 85 C I OH mA VOH V ...

Page 141: ...CC Figure 99 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 THRESHOLD VOLTAGE V VCC I O PIN INPUT THRESHOLD VOLTAGE vs VCC TA 25 C 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2 7 4 0 5 0 IINPUT HYSTERESIS V VCC I O PIN INPUT HYSTERESIS vs VCC TA 25 C ...

Page 142: ...ter2 Counter Register page 44 22 42 OCR2 Timer Counter2 Output Compare Register page 44 21 41 WDTCR WDTOE WDE WDP2 WDP1 WDP0 page 58 20 40 UBRRHI UBRR1 11 8 UBRR0 11 8 page 76 1F 3F EEARH EEAR8 page 60 1E 3E EEARL EEPROM Address Register Low Byte page 60 1D 3D EEDR EEPROM Data Register page 60 1C 3C EECR EERIE EEMWE EEWE EERE page 61 1B 3B PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 POR...

Page 143: ...ved I O memory addresses should never be written 2 Some of the status flags are cleared by writing a logical 1 to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with registers 00 to 1F only ...

Page 144: ...l Multiply Signed with Unsigned R1 R0 Rd x Rr 1 Z C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC k 1 None 2 IJMP Indirect Jump to Z PC Z None 2 JMP k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC k 1 None 3 ICALL Indirect Call to Z PC Z None 3 CALL k Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd Rr Compare S...

Page 145: ... Post inc Y Rr Y Y 1 None 2 ST Y Rr Store Indirect and Pre dec Y Y 1 Y Rr None 2 STD Y q Rr Store Indirect with Displacement Y q Rr None 2 ST Z Rr Store Indirect Z Rr None 2 ST Z Rr Store Indirect and Post inc Z Rr Z Z 1 None 2 ST Z Rr Store Indirect and Pre dec Z Z 1 Z Rr None 2 STD Z q Rr Store Indirect with Displacement Z q Rr None 2 STS k Rr Store Direct to SRAM k Rr None 2 LPM Load Program Me...

Page 146: ...s Complement Overflow V 1 V 1 CLV Clear Two s Complement Overflow V 0 V 1 SET Set T in SREG T 1 T 1 CLT Clear T in SREG T 0 T 1 SEH Set Half carry Flag in SREG H 1 H 1 CLH Clear Half carry Flag in SREG H 0 H 1 NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 3 WDR Watchdog Reset see specific descr for WDR timer None 1 Instruction Set Summary Continued Mnemonic Operand...

Page 147: ... 44A 40P6 Commercial 0 C to 70 C ATmega161 4AI ATmega161 4PI 44A 40P6 Industrial 40 C to 85 C 8 4 0 5 5V ATmega161 8AC ATmega161 8PC 44A 40P6 Commercial 0 C to 70 C ATmega161 8AI ATmega161 8PI 44A 40P6 Industrial 40 C to 85 C Package Type 44A 44 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 40P6 40 lead 0 600 Wide Plastic Dual Inline Package PDIP ...

Page 148: ...5 0 030 0 45 0 018 0 15 0 006 0 05 0 002 0 20 0 008 0 09 0 004 0 7 0 80 0 0315 BSC PIN 1 ID 0 45 0 018 0 30 0 012 PIN 1 Controlling dimension millimetter 44A 44 lead Thin 1 0mm Plastic Quad Flat Package TQFP 10x10mm body 2 0mm footprint 0 8mm pitch Dimension in Millimeters and Inches JEDEC STANDARD MS 026 ACB REV A 04 11 2001 ...

Page 149: ...88 0 625 15 24 0 600 1 65 0 065 1 27 0 050 17 78 0 700 MAX 0 38 0 015 0 20 0 008 2 54 0 100 BSC 3 56 0 140 3 05 0 120 SEATING PLANE 4 83 0 190 MAX 48 26 1 900 REF 0º 15º 40P6 40 lead Plastic Dual Inline Parkage PDIP 0 600 wide Demension in Millimeters and Inches JEDEC STANDARD MS 011 AC Controlling dimension Inches REV A 04 11 2001 ...

Page 150: ...41 26 426 5555 FAX 41 26 426 5500 Asia Atmel Asia Ltd Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721 9778 FAX 852 2722 1369 Japan Atmel Japan K K 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Atmel Colorado Springs 1150 E Cheyenne Mtn Blvd Colorado Springs CO 80906 TEL 719 576 3300 FAX 719 5...

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