92
ATmega161(L)
1228B–09/01
Port B Schematics
Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 57.
Port B Schematic Diagram (Pins PB0 and PB1)
PBn
DDBn
PORTBn
COMP. MATCH x
COMx0
COMx1
WP:
WD:
RL:
RP:
RD:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
FOCx
PWMx
n: 0,1
x: 0,2
CSn2 CSn1 CSn0