33
ATmega161(L)
1228B–09/01
• Bit 1
–
TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$016) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0
–
OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $014) is executed if a Compare0 match in Timer/Counter0 occurs, i.e., when the
OCF0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7
–
TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE1
(Ti m e r/ Co u nt e r1 O ver flo w I nt e rru p t E n ab l e ), a n d TOV 1 ar e s e t ( on e ), t h e
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
• Bit 6
–
OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare match InterruptA Enable) and OCF1A are set (one), the
Timer/Counter1 Compare A match Interrupt is executed.
• Bit 5
–
OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare match InterruptB Enable) and OCF1B are set (one), the
Timer/Counter1 Compare B match Interrupt is executed.
• Bit 4
–
TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2
(T i m e r / C o u n t e r 2 O v e rf l o w I n t e rr u p t E n a b l e ) a n d T OV 2 a r e s e t ( o n e ), t h e
Timer/Counter2 Overflow interrupt is executed.
Bit
7
6
5
4
3
2
1
0
$38 ($58)
TOV1
OCF1A
OCIFB
TOV2
ICF1
OCF2
TOV0
OCF0
TIFR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
