31
ATmega161(L)
1228B–09/01
General Interrupt Mask
Register – GIMSK
• Bit 7
–
INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or is level-sensed.
Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
The corresponding interrupt of External Interrupt Request 1 is executed from program
memory address $004. See also “External Interrupts”.
• Bit 6
–
INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or is level-sensed.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $002. See also “External Interrupts.”
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control2 bit (ISC02 in the
Extended MCU Control Register [EMCUCR]) defines whether the external interrupt is
activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-
rupt request even if INT2 is configured as an output. The corresponding interrupt of
External Interrupt Request 2 is executed from program memory address $006. See also
“External Interrupts.”
• Bits 4..0
–
Res: Reserved Bits
These bits are reserved bits in the ATmega161 and always read as zero.
General Interrupt Flag
Register – GIFR
• Bit 7
–
INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the
interrupt vector at address $004. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bit 6
–
INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
interrupt vector at address $002. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical “1” to it.
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
INT2
–
–
–
–
–
GIMSK
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
INTF2
–
–
–
–
–
GIFR
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
