[AK4493]
017012230-E-00
2017/12
- 78 -
[2] Power ON/OFF by PW bit
All circuits except control register, bias generation circuit and LDO (only when the LDOE pin =
“H”) stop
operation by setting PW bit to
“0”. In this case, control register access is available. The analog output
goes to floating state (Hi-Z).
shows power ON/OFF sequence by PW bit.
Internal
State
PW bit
Power-off
Normal Operation
GD
GD
“0” data
DAC Out
(Analog)
DAC In
(Digital)
(1)
(3)
(3)
(1)
(2)
Hi-Z
Normal Operation
RSTN bit
(4)
DZFL/DZFR
External
MUTE
(6)
Mute ON
(5)
(5)
Note:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit
= “0”.
(3) Click noise occurs on an edge of PW bit.
This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4493 is power off (PW bit =
“0”). This figure shows
the seuqnece when DZFE bit =
“1”, DZFB bit = “0” and DZFM bit = “0”.
(5) It takes 4~5/fs until a power down instruction is valid when writing PW bit and it takes 1~2/fs when
releasing the power down.
(6) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system
performance.
Figure 63. Power ON/OFF Timing Example
