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[AK4493]

017012230-E-00

2017/12

- 5 -

4. Block Diagram

MCLK

SDATA/DSDL/DINL

SMUTE/CSN

BICK/DCLK/BCK

SD/CCLK/SCL

SLOW/CDTI/SDA

VSSR

VDDR

PDN

AVDD

SCF

SCF

Clock

Divider

DVSS

DVDD

SSLOW/WCK

ACKS/

CAD1

PSN

DIF0/
DZFL

DIF2/
CAD0

VSSL

VDDL

VCML

AOUTRN

VCMR

VREFHL
VREFLL

VREFLR
VREFHR

AVSS

AOUTLP

AOUTLN

AOUTRP

PCM

Data

Interface

External

DF

Interface

Control

Register

Bias

Vref

LRCK/DSDR/DINR

DEM0

DIF1/
DZFR

DATT

Soft Mute



Modulator

Volume bypass

DSDD bit

“1”

Normal path
DSDD bit

“0”

I2C/INV

LDO

LDOE

TVDD

De-emphasis

&

Interpolator

DSD Data

Interface

&

DSD Filter

MCLK

Stop

Detection

TESTE

Figure 1. Block Diagram

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Summary of Contents for AK4493

Page 1: ...z 768kHz 32 bit 8x Digital Filter Short Delay Sharp Roll off GD 6 0 fs Short Delay Slow Roll off GD 5 0 fs Sharp Roll off Slow Roll off Low Dispersion Short Delay Filter Super Slow Roll off High Toler...

Page 2: ...AK4493 017012230 E 00 2017 12 2 Digital Input Level CMOS Package 48 pin LQFP...

Page 3: ...sion Mode Switching Timing 38 System Clock 39 Audio Interface Format 45 Digital Filter 55 De emphasis Filter PCM 55 Output Volume PCM DSD and EXDF Modes Register Control Mode only 56 Gain Adjustment F...

Page 4: ...AK4493 017012230 E 00 2017 12 4 12 Ordering Guide 103 Ordering Guide 103 13 Revision History 103 IMPORTANT NOTICE 104...

Page 5: ...IF0 DZFL DIF2 CAD0 VSSL VDDL VCML AOUTRN VCMR VREFHL VREFLL VREFLR VREFHR AVSS AOUTLP AOUTLN AOUTRP PCM Data Interface External DF Interface Control Register Bias Vref LRCK DSDR DINR DEM0 DIF1 DZFR DA...

Page 6: ...22 21 20 19 18 17 16 15 14 13 Top View 48 12 24 25 AK4493 SDATA DSDL DINL SMUTE CSN LRCK DSDR DINR SSLOW WCK SD CCLK SCL SLOW CDTI SDA DIF0 DZFL DIF1 DZFR DEM0 LDOE INV I2C PSN VREFHR VREFHR OUTRP VR...

Page 7: ...iated When returning L the output mute releases CSN I Chip Select Pin in Register Control Mode I2C L 8 SD I Digital filter setting in Pin Control Mode CCLK I Control Data Clock Pin in Register Control...

Page 8: ...Lch Analog Power Supply Pin 4 75 5 25V 34 VDDL Lch Analog Power Supply Pin 4 75 5 25V 35 AOUTLN O Lch Negative Analog Output Pin 36 AOUTLP O Lch Positive Analog Output Pin 37 NC No internal bonding Co...

Page 9: ...log AOUTLP AOUTLN Open AOUTRP AOUTRN Open Digital WCK DEM0 Connect to DVSS TESTE Connect to DVSS or Open DZFL DZFR Open 2 DSD Mode Classification Pin Name Status Analog AOUTLP AOUTLN Open AOUTRP AOUTR...

Page 10: ...V V V V V V V Voltage Reference H voltage reference Note 6 L voltage reference VREFHL R VREFLL R 0 3 0 3 VDDL R 0 3 Or 6 0 0 3 V V Input Current Any Pin Except Supplies IIN 10 mA Digital Input Voltage...

Page 11: ...1 98 5 25 3 6 3 6 5 25 V V V V V V V Voltage Reference Note 8 H voltage reference L voltage reference VREFHL R VREFLL R VDDL R 0 5 VSSL R VDDL R V V Note 4 All voltages with respect to ground Note 8...

Page 12: ...s 000 Note 14 2 65 2 8 2 95 Vpp GC 2 0 bits 100 Note 15 3 55 3 75 3 95 Vpp Load Resistance Note 16 450 Load Capacitance Note 16 25 pF Note 11 Measured by Audio Precision APx555 Averaging mode Note 12...

Page 13: ...nt Normal operation PDN pin H VDDL R total 33 50 mA VREFHL R 1 1 5 mA AVDD 1 1 5 mA TVDD LDOE pin H fs 44 1kHz 9 13 5 mA fs 96kHz 15 22 5 mA fs 192kHz 23 34 5 mA LDOE pin L 1 1 5 mA DVDD LDOE pin L fs...

Page 14: ...stics are not guaranteed with DSD512 datastream Note 21 The peak level of DSD signal should be in the range of 25 75 duty according to the SACD format book Scarlet Book Note 22 The output level is ass...

Page 15: ...L Parameter Symbol Min Typ Max Unit Digital Filter Frequency Response Note 26 0 01dB 6 0dB 0 48 0 43 5 kHz kHz Passband Note 27 PB 0 43 5 kHz Stopband Note 27 SB 52 5 kHz Passband Ripple Note 28 PR 0...

Page 16: ...gain amplitude of first step interpolator which is 4 times oversampling filter in pass band width Note 29 The calculating delay time which occurred by digital filtering This time is from setting the 1...

Page 17: ...or SSLOW pin L Parameter Symbol Min Typ Max Unit Digital Filter Frequency Response Note 26 0 01dB 6 0dB 0 45 6 17 6 kHz kHz Passband Note 30 PB 0 17 6 kHz Stopband Note 30 SB 85 4 kHz Passband Ripple...

Page 18: ...AK4493 017012230 E 00 2017 12 18 Figure 5 Slow Roll off Filter Frequency Response Figure 6 Slow Roll off Filter Passband Ripple...

Page 19: ...L SSLOW bit 0 or SSLOW pin L Parameter Symbol Min Typ Max Unit Digital Filter Frequency Response Note 26 0 01dB 6 0dB 0 48 0 43 5 kHz kHz Passband Note 31 PB 0 43 5 kHz Stopband Note 31 SB 52 5 kHz P...

Page 20: ...AK4493 017012230 E 00 2017 12 20 Figure 7 Short Delay Sharp Roll off Filter Frequency Response Figure 8 Short Delay Sharp Roll off Filter Passband Ripple...

Page 21: ...SSLOW bit 0 or SSLOW pin L Parameter Symbol Min Typ Max Unit Digital Filter Frequency Response Note 26 0 01dB 6 0dB 0 45 6 17 6 kHz kHz Passband Note 29 PB 0 17 6 kHz Stopband Note 29 SB 85 4 kHz Pass...

Page 22: ...AK4493 017012230 E 00 2017 12 22 Figure 9 Short Delay Slow Roll off Filter Frequency Response Figure 10 Short Delay Slow Roll off Filter Passband Ripple...

Page 23: ...SSLOW pin H Parameter Symbol Min Typ Max Unit Digital Filter Frequency Response Note 26 0 05dB 6 0dB 0 48 0 40 1 kHz kHz Passband Note 32 PB 0 40 1 kHz Stopband Note 32 SB 55 9 kHz Passband Ripple No...

Page 24: ...AK4493 017012230 E 00 2017 12 24 Figure 11 Low Dispersion Short Delay Filter Frequency Response Figure 12 Low Dispersion Short Delay Filter Passband Ripple...

Page 25: ...ve is input Note 35 The frequency 20kHz 50kHz 100kHz or 150 kHz is doubled in DSD128 speed DSDSEL 1 0 bits 01 is quadrupled in DSD256 speed DSDSEL 1 0 bits 10 and is 8x in DSD512 speed DC Characterist...

Page 26: ...q fso fsh Duty 8 54 108 45 384 768 54 108 216 55 kHz kHz kHz kHz kHz TDM128 mode TDM 1 0 bits 01 Normal Speed Mode Double Speed Mode Quad Speed Mode High time Low time fsn fsd fsq tLRH tLRL 8 54 108 1...

Page 27: ...38 LRCK Edge to BICK Note 38 SDATA Hold Time SDATA Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1 128fsn 1 128fsd 1 128fsq 14 14 14 14 5 5 nsec nsec nsec nsec nsec nsec nsec nsec nsec TDM...

Page 28: ...d DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDL R Note 39 tDCK tDCKL tDCKH tDDD 72 72 10 1 128fs 10 nsec nsec nsec nsec DSD256 DSDSEL 1 0 bits 10 DCLK Period DCLK Pulse Width Low DCLK P...

Page 29: ...ition SDA Hold Time from SCL Falling Note 41 SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike N...

Page 30: ...2017 12 30 Timing Diagram 1 fCLK tCLKL VIH tCLKH MCLK VIL dCLK tCLKH x fCLK tCLKL x fCLK 1 fs VIH LRCK VIL tLRL tLRH tBCK tBCKL VIH tBCKH BICK VIL tWCK tWCKL VIH tWCKH WCK VIL tB tBL VIH tBH BCK VIL...

Page 31: ...31 tLRB LRCK VIH BICK VIL VIH VIL tBLR tSDS SDATA VIH VIL tSDH Figure 14 Audio Interface Timing PCM Mode tWB WCK VIH BCK VIL tDS VIH DINL DINR VIL tDH VIH VIL tBW Figure 15 Audio Interface Timing Ext...

Page 32: ...DSD64 DSD128 DSD256 Mode VIH DCLK VIL VIH DSDL DSDR VIL tDCKH tDCKL tDCK tDDH tDDS DSD Audio Interface Timing DSD512 Mode Figure 16 Audio Interface Timing DSD Normal Mode DCKB bit 0 VIH DCLK VIL tDDD...

Page 33: ...017 12 33 tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R W A4 tCCKL tCCKH tCDS tCDH tCCK Figure 18 WRITE Command Input Timing CSN VIH CCLK VIL VIH CDTI VIL VIH VIL D3 D2 D1 D0 tCSW tCSH Figure 19...

Page 34: ...230 E 00 2017 12 34 tHIGH SCL SDA VIH tLOW tBUF tHD STA tR tF tHD DAT tSU DAT tSU STA Stop Start Start Stop tSU STO VIL VIH VIL tSP Figure 20 I2 C Bus Mode Timing tAPD tRPD PDN VIL Figure 21 Power Dow...

Page 35: ...lable functions of each control mode and Table 3 shows available functions in PCM DSD EXDF mode Table 1 Pin Register Control Mode Select PSN pin Control Mode L Register Control Mode H Pin Control Mode...

Page 36: ...at in PCM Mode 32bit MSB 00H DIF 2 0 Y Audio Data Interface Format in EXDF Mode 32bit LSB 00H DIF 2 0 Y TDM Interface Format Normal Mode 0AH TDM 1 0 Y Attenuation Level 0dB 03 04H ATTL R 7 0 Y Y Y Dat...

Page 37: ...ed during reset state by setting RSTN bit 0 RSTN bit should not be changed for 4 fs after switching these modes It takes 2 fs 3 fs for data mode switching External digital filter I F can be selected b...

Page 38: ...anged to PCM EXDF from DSD mode RSTN bit D A Data D A Mode 4 fs 0 PCM or EXDF Data DSD Data PCM or EXDF Mode DSD Mode L Figure 22 D A Mode Switching Timing from PCM EXDF to DSD RSTN bit D A Data D A M...

Page 39: ...control registers bias generation circuit and internal LDO if LDOE pin H of the AK4493 are automatically placed in power down state when MCLK is stopped for more than 1us during normal operation PDN...

Page 40: ...48 0kHz N A N A N A N A N A N A 88 2kHz N A N A N A N A N A N A Double 96 0kHz N A N A N A N A N A N A 176 4kHz N A N A N A N A 22 5792 33 8688 Quad 192 0kHz N A N A N A N A 24 5760 36 8640 384kHz N...

Page 41: ...gister Control Mode LRCK MCLK MHz Sampling Speed Fs 16fs 32fs 48fs 64fs 96fs 128fs 32 0kHz N A N A N A N A N A N A Normal 44 1kHz N A N A N A N A N A N A 48 0kHz N A N A N A N A N A N A 88 2kHz N A N...

Page 42: ...A N A 24 5760 384kHz N A N A 24 576 36 864 N A Oct 768kHz 24 576 36 864 N A N A N A Hex Table 16 System Clock Example Auto Setting Mode in Register Control Mode LRCK MCLK MHz Sampling Speed fs 192fs 2...

Page 43: ...68fs 64fs 128fs 256fs 512fs The AK4493 supports DSD data stream rates of 2 8224MHz 64fs 5 6448MHz 128fs 11 2896MHz 256fs and 22 5792MHz 512fs for 44 1kHz base rates Any base rate in the range 30kHz 48...

Page 44: ...ly placed in power down state when MCLK edge is not detected for more than 1us during normal operation PDN pin H and the analog output becomes Hi Z state The power down state is released and the AK449...

Page 45: ...he unused LSBs TDM128 Mode TDM 1 0 bits 01 Register Control Mode only 4ch Data is shifted in via the SDATA pin using BICK and LRCK inputs Data slot can be selected by SDS 2 0 bits Table 23 BICK is fix...

Page 46: ...0 32 bit MSB justified H L 128fs Figure 32 13 1 1 1 32 bit I2 S compatible L H 128fs Figure 33 TDM256 14 1 0 0 1 0 24 bit MSB justified H L 256fs Figure 35 15 0 1 1 24 bit I2 S compatible L H 256fs F...

Page 47: ...0 Lch Data Rch Data Figure 25 Mode 0 Timing SDATA LRCK BICK 64fs 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 Mode 1 Don t care Don t care 19 MSB 0 LSB SDATA Mode 4 23 MSB 0 LSB 20 19 0 20 19 0 D...

Page 48: ...1 0 31 1 BICK 64fs SDATA 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31 MSB 0 LSB 8 0 1 8 0 1 Lch Data Rch Data 0 31 1 Figure 29 Mode 5 Timing LRCK BICK 12...

Page 49: ...31 21 20 19 9 0 21 20 19 31 MSB 0 LSB 8 1 2 8 1 2 Lch Data Rch Data Figure 31 Mode 7 Timing LRCK BICK 128fs 128 BICK L1 32 BICK R1 32 BICK 32 BICK 32 BICK SDATA 22 0 22 0 23 23 22 23 Mode8 SDATA 30 0...

Page 50: ...A 31 30 0 30 31 31 30 0 SDATA Mode14 Mode17 18 32 BICK 32 BICK 32 BICK 32 BICK Figure 35 Mode 14 17 18 Timing LRCK BICK 256fs 23 0 L1 32 BICK 256 BICK 23 0 R1 32 BICK 23 32 BICK 32 BICK SDATA Mode15 3...

Page 51: ...0 23 24 Timing BICK 512fs SDATA Mode21 LRCK 512 BICK 22 2 0 23 22 0 23 SDATA Mode25 L1 32 BICK R1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BIC...

Page 52: ...selected by SDS 2 0 bits Register Control Mode only as shown in Table 23 LRCK SDATA R1 L1 Figure 41 Data Slot in Normal Mode SDATA R1 L1 LRCK 128 BICK R2 L2 Figure 42 Data Slot in TDM128 Mode SDATA R1...

Page 53: ...R channel data must be input to the DSDL pin and the DSDR pin respectively by synchronizing to DCLK In case of DSD mode the settings of DIF2 0 pins and DIF 2 0 bits are ignored The frequency of DCLK i...

Page 54: ...put Format 0 0 0 0 16 bit LSB justified 1 0 0 1 N A 2 0 1 0 16 bit LSB justified 3 0 1 1 N A 4 1 0 0 24 bit LSB justified 5 1 0 1 32 bit LSB justified 6 1 1 0 24 bit LSB justified default 7 1 1 1 32 b...

Page 55: ...by the DSDF bit Table 26 shows the cutoff frequency fs 44 1 kHz The cutoff frequency tracks the sampling frequency fs Do not set GC 2 0 bits to 100 when DSDD bit 0 and DSDF bit 1 Otherwise a pop noise...

Page 56: ...1 0 bits Table 29 When changing output levels between Mode0 3 it is executed in soft transition thus no switching noise occurs during these transitions Register setting values will be kept even switc...

Page 57: ...he DZFL R pin when setting DZFE bit 1 and DDMOE bit 0 When the input data at each channel is continuously zeros for 8192 LRCK cycles the DZF pin of each channel outputs zero detection flag independent...

Page 58: ...DMR DML is output from the DZFL R pin when DDMOE bit 1 The output signal setting of the DZFL R pin is shown in Table 33 The output polarity is inverted when DZFB bit 1 Table 33 Output Signal Setting...

Page 59: ...Lch In Invert Lch In 1 1 Lch In Invert Lch In Invert 1 1 0 0 Rch In Rch In 0 1 Rch In Rch In Invert 1 0 Rch In Invert Rch In 1 1 Rch In Invert Rch In Invert Table 35 Output Select Pin Control Mode IN...

Page 60: ...nnel This analog output mute transition is depending on the setting of DSDD bit that selects DSD playback path Table 39 When DSDD bit 1 Volume Bypass the output data of DSD filter is changed to Zero d...

Page 61: ...ult 1 Volume Bypass Rapidly Full scale Detect flag DML or DMR DSD Data DSD Full scale Data DSD Data AOUT DSDD bit 1 AOUT DSDD bit 0 RSTN bit Internal RSTN bit 3 4 fs DSD Full scale Data 2 1 2 2 1 Note...

Page 62: ...et by DDMT 1 0 bits after releasing internal reset 2 Analog output is forced to zero VCML R level when the AK4493 detects full scale data 3 Analog output delays for the period set by DDMT 1 0 bits 8DC...

Page 63: ...ta is matched with one of 01101001 01101001 01010101 01010101 and 00110011 00110011 codes twice continuously The AK4493 detects PCM mode when the input data is matched with either 00000000 00000000 or...

Page 64: ...e continuously 00000000 00000000 or 11111111 11111111 PCM Mode Table 42 Mode Detection Conditions when EXDF bit 1 Number of Pulse of BCK DCLK 3 In WCK 6 Cycle Detection Result 256 BCK DCLK pulse numbe...

Page 65: ...and then ADP bit is changed on a rising edge of input signal of the LRCK DSDR pin Mode detection is executed even when there is no MCLK input 3 When DSD mode is changed the AK4493 executes internal r...

Page 66: ...ecutes internal reset for 3 4 fs automatically 4 The AK4493 starts mode detection when input data of both channels are continuously zero for the period set by ADPT 1 0 bits and it finishes mode detect...

Page 67: ...T 1 0 bits and it finishes mode detection when a data that is not zero is input 3 Mode detection is performed by monitoring input signal code pattern of the LRCK DSDR pin It is executed for 34 cycles...

Page 68: ...e switching from DSD to EXDF mode Mode detection is executed even when there is no MCLK input 4 When DSD mode is changed the AK4493 executes internal reset for 3 4 fs automatically 5 The AK4493 starts...

Page 69: ...n there is no MCLK input 4 According to power up sequence reset is released when MCLK is input after setting RSTN bit 1 5 The AK4493 starts mode detection when input data of both channels are continuo...

Page 70: ...ADPT 1 0 bits and it finishes mode detection when a data that is not zero is input 3 Mode detection is performed by monitoring input clock of the WCK and BCK DCLK pins It takes 256DCLK cycles for mode...

Page 71: ...d to ATT level by the same cycle The soft mute is effective for changing the signal source without stopping the signal transmission SMUTE pin or SMUTE bit Attenuation DZFL R pin ATT_Level AOUTL R 8192...

Page 72: ...the error detection status Table 46 Error Detection No Error Detection Error Detection Conditions 1 LDO Overvoltage Detection The AK4493 detects an error when the output voltage of the LDO pin exceed...

Page 73: ...nternal LDO LDOE pin H PDN pin Power TVDD AVDD VDDL R Normal Operation DAC Clock In MCLK LRCK BICK DAC In Digital DAC Out Analog External Mute Mute ON 6 0 data GD 3 5 GD 5 Mute ON 0 data Internal Stat...

Page 74: ...wn switch is on after power up if the LDOE pin L The internal circuit will start operation in 1us max after the shutdown switch is ON 3 The analog output corresponding to the digital input has group d...

Page 75: ...wer TVDD AVDD VDDL R Reset Reset Reset 11 Hi Z Hi Z Reset Notes 1 The PDN pin must be L when start supplying AVDD TVDD and VDDL R It must be held L for more than 150ns after AVDD TVDD and VDDL R are p...

Page 76: ...al circuit will start operation in 1us max after the shutdown switch is ON 3 The analog output corresponding to the digital input has group delay GD 4 Analog outputs are floating Hi Z in power down mo...

Page 77: ...min during operation PDN pin H In this case the analog output goes floating state Hi Z The AK4493 returns to normal operation if PW bit and RSTN bit are 1 after starting to supply MCLK again The zero...

Page 78: ...DZFR External MUTE 6 Mute ON 5 5 Note 1 The analog output corresponding to the digital input has group delay GD 2 The analog output is floating Hi Z state when PW bit 0 3 Click noise occurs on an edge...

Page 79: ...2 3 fs 5 3 4 fs 5 6 Notes 1 The analog output corresponding to the digital input has group delay GD 2 The analog output is VCML R voltage when RSTN bit 0 3 Click noise occurs on an edge of internal RS...

Page 80: ...by setting SYNCE bit 0 in register control mode Figure 65 shows a synchronizing sequence when the input data is 0 for 8192 times continuously Figure 66 shows a synchronizing sequence by RSTN bit SMUTE...

Page 81: ...is valid During the DZFL R pin H 2 Internal data is fixed to 0 forcibly for 2 to 3 fs when the internal counter is reset 3 Since the analog output corresponding to digital input has group delay GD it...

Page 82: ...data MSB first 8 bits The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK The writing of data is valid when CSN The clock speed of CCLK is 5MHz max Setting...

Page 83: ...e data after the second byte contains control data The format is MSB first 8bits Figure 71 The AK4493 generates an acknowledge after each byte is received Data transfer is always terminated by a STOP...

Page 84: ...byte of data to the address set by the internal address counter and increments the internal address counter by 1 If the master does not generate an acknowledge but generates a stop condition instead...

Page 85: ...tion and Stop Condition SCL FROM MASTER acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 1 9 8 START CONDITION not acknowledge clock pulse for acknowledgement S 2 Figure 75 Acknowledge I...

Page 86: ...0 0 13H Reserved 0 0 0 0 0 0 0 0 14H Reserved 0 0 0 0 0 0 0 0 15H Control 8 ADPE ADPT1 ADPT0 0 0 0 0 0 Notes In 3 wire serial control mode the AK4493 does not support read commands The AK4493 supports...

Page 87: ...0 0 0 0 DFS2 DFTHR 06H Control5 DDM DML DMR DMC DMRE DSDD1 DSDD0 DSDSEL 07H Control6 0 0 0 0 0 0 0 SYNCE 08H Sound Control 0 0 0 0 0 SC2 SC1 SC0 09H Reserved 0 0 0 0 0 0 0 0 AK4497 Register Map Refere...

Page 88: ...mal Operation DIF 2 0 Audio Data Interface Modes Table 22 Initial value is 110 Mode6 32bit MSB justified ECS EXDF mode clock setting Table 21 0 WCK 768kHz mode default 1 WCK 384kHz mode EXDF External...

Page 89: ...noise occurs when DFS 2 0 bits are changed SD Short Delay Filter Enable Table 25 0 Traditional filter SSLOW 0 Super Slow Roll off SSLOW 1 SD 0 1 Short delay filter default SSLOW 0 Low Dispersion Filt...

Page 90: ...ONO mode L channel output R channel data R channel data output L channel data DZFB Inverting Enable of DZF Table 32 0 DZF pin goes H at Zero Detection default 1 DZF pin goes L at Zero Detection MONO M...

Page 91: ...p mute Data Attenuation FFH 0dB default FEH 0 5dB FDH 1 0dB 02H 126 5dB 01H 127 0dB 00H MUTE Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Control 4 INVL INVR 0 0 0 0 DFS2 SSLOW R W R W R W R W R W R...

Page 92: ...0 Normal Path default 1 Volume Bypass DDMT 1 0 DSD Signal Full scale Detection Time Setting Table 38 DDMOE Output Setting of the DMR L Pins for DSD Full scale Detection Table 33 DMR DML This register...

Page 93: ...d Control Table 36 Table 37 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H DSD2 0 0 0 0 0 0 DSDF DSDSEL1 R W R R R R W R W R W R W R W Default 0 0 0 0 0 0 0 0 DSDSEL1 DSD Sampling Speed Control DSDF C...

Page 94: ...Channel 0 Normal 1 Output Data of Other Slot Table 23 ATS 1 0 Transition Time between Set Values of ATTL R 7 0 bits Table 30 The default value is 00 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH Rese...

Page 95: ...ADPE ADPT1 ADPT0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 ADPT 1 0 Time until PCM DSD mode detection when input data becomes zero PCM EXDF DSD modes Table 40 ADPE Automati...

Page 96: ...TRP AOUTLP 34 35 36 48 47 46 45 NC NC 12 0 1 1 Digital 1 8V Reference Voltage 5 0V Reference Voltage 0V Reference Voltage 5 0V Reference Voltage 0V Note BICK 64fs LRCK fs Power lines of AVDD TVDD VDDL...

Page 97: ...erence Voltage 5 0V Reference Voltage 0V Reference Voltage 5 0V Reference Voltage 0V Note BICK 64fs LRCK fs Power lines of AVDD TVDD VDDL and VDDR should be distributed separately with low impedance o...

Page 98: ...of fc 17Hz will be composed with the 470 F capacitor and the 10 resistor It removes signal frequency noise from other power supply lines No load current may be drawn from the VCML R pin since VCML R i...

Page 99: ...l LPF Circuit Example 1 Gain 1kHz Typ 8 75 dB Frequency Response ref 1kHz Typ 20kHz 0 02 dB 40kHz 0 13 dB 80kHz 1 34 dB 910 910 91 300 27 300 Vop 1 5n Vop AOUTLN R N AOUTLP RP Analog Out AK4493 OPA161...

Page 100: ...Hz typ Q 0 67 typ Table 50 Frequency Response of External LPF Circuit Example 3 Gain 1kHz Typ 9 54 dB Frequency Response ref 1kHz Typ 20kHz 0 01 dB 40kHz 0 07 dB 80kHz 0 34 dB 182 100 91 10k 12n 825 1...

Page 101: ...ial Terminal Finish Package Molding Compound Epoxy Halogen Br and Cl free Lead Frame Material EFTEC 64T Terminal Surface Treatment Solder Pb free plate 0 09 0 20 1 00 12 13 24 25 36 37 48 7 00 9 00 9...

Page 102: ...AK4493 017012230 E 00 2017 12 102 Marking AK4493EQ 0VT XXXXXXX 1 48 AKM 1 Pin 1 indication 2 Date Code XXXXXXX 7 digits 3 Marking Code AK4493EQ 4 AKM Logo...

Page 103: ...0 E 00 2017 12 103 12 Ordering Guide Ordering Guide AK4493EQ 40 85 C 48 pin LQFP 0 5mm pitch AKD4493 Evaluation Board for AK4493 13 Revision History Date Y M D Revision Reason Page Contents 17 12 05 0...

Page 104: ...AKM in writing 3 Though AKM works continually to improve the Product s quality and reliability you are responsible for complying with safety standards and for providing adequate designs and safeguard...

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