[AK4493]
017012230-E-00
2017/12
- 97 -
10.2 pin control mode, LDO enable.
Analog 5.0V
Ceramic Capacitor
+
Electrolytic Capacitor
Rch
LPF
Rch
Mute
Rch Out
Digital 3.3V
+
0.1
µ
10
µ
Analog 3.3V
0.1
µ
10
µ
DSP
Micro-
Controller
+
0.1
µ
10
µ
Lch
LPF
Lch
Mute
Lch Out
PDN
T
V
D
D
1
BICK
44
2
SDATA
3
LRCK
4
SSLOW
5
SMUTE
6
SD
7
SLOW
8
DIF0
9
DIF1
10
DIF2
11
PSN
33
AOUTLN
A
K4493
13
14
15
16
17
19
20
21
22
IN
V
D
E
M0
L
D
OE
A
C
K
S
V
R
E
FH
R
V
R
E
FH
R
V
R
E
FLR
V
R
E
FLR
V
CM
R
NC
32
VDDL
31
VDDL
30
VSSL
29
VSSL
28
27
VSSR
N
26
VSSR
25
VDDR
VDDR
AOUTRN
D
V
S
S
43
MCL
K
42
AVSS
41
A
V
D
D
40
V
R
E
FH
L
39
V
R
E
FH
L
38
V
R
E
FLL
37
V
R
E
FLL
V
C
ML
0.1
µ
470
µ
10
µ
0.1
µ
10
µ
+
10
µ
470
µ
0.1
µ
DVDD
23
24
18
TE
S
TE
AOUTRP
AOUTLP
34
35
36
48
47
46
45
NC
NC
12
0.1
µ
1
µ
+
+
+
+
+
+
Reference Voltage 5.0V
Reference Voltage 0V
Reference Voltage 5.0V
Reference Voltage 0V
Note:
- BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately with low
impedance of regulators, etc. maintained.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog
ground should have low impedance as a solid pattern. THD+N characteristics will degrade if there
are impedances between each VSS.)
- It is recommended to input MCLK via a damping resistor. Without the resistor, there is a possibility
that THD+N characteristic degrades because of high-frequency noise of MCLK.
- All input pins except pull-down/pull-up pins should not be allowed to float.
- For DVDD pin, 1µF capacitor(
±
50%, including temperature characteristics) should be connected.
Figure 78. Typical Connection Diagram
(AVDD = TVDD = 3.3V, VDDL/R = VREFHL/R = 5.0V, LDOE pin =
“H”, Pin Control Mode)
