[AK4493]
017012230-E-00
2017/12
- 63 -
■
Automatic Mode Switching Function (PCM/EXDF
⇔
DSD Mode; Register Control Mode
only)
The AK4493 has automatic mode switching function that determines DSD or PCM/EXDF mode from input
signals of the BICK/BCK/DCLK pin (#3), LRCK/DSDR pin (#4) and WCK pin (#6). This function is
available by setting ADPE bit =
“1” when the PDN pin = “H” and the PSN pin = “L”. ADPE bit must be set
while PW bit or RSTN bit =
“0”. DP bit is for manual setting. It will be ignored when ADPE bit is “1”. The
result of automatic mode detection can be readout by ADP bit. This readout function of ADP bit is invalid
and
“0” data is readout when ADPE bit = “0”. Group delay will be 18/fs longer in PCM/EXDF mode and
136~1032DCLK cycle longer according to full-scale detection time setting by DDMT[1:0] bits in DSD
mode when setting ADPE bit =
“1”
.
PCM mode and EXDF mode are not distinguished. This
function does not support DSD phase modulation format and edge inversion function of DSD receiving
data (DCKB bit =
“1”). EXDF bit must be set while PW bit or RSTN bit = “0”.
If one of the five conditions shown below is satisfied, the AK4493 executes mode detection. The AK4493
keeps previous mode instead of executing mode detection if any condition is not satisfied.
1
．
Input data of both channels are zero for a period set by ADPT[1:0] bits (
2
．
Output data of both channels are zero for a period set by ADPT[1:0] bits because of attenuation.
3
．
Input data of both channels are full-scale for a period set by DDMT[1:0] bits in DSD mode.
4
．
PW bit =
“0”
5
．
RSTN bit =
“0”
When EXDF bit =
“0”, the AK4493 execute mode detection by comparing the input signal to the
LRCK/DSDR pin (#4) to fixed code patterns. There are five fixed code patterns:
“01101001 01101001”,
“01010101 01010101”, “00110011 00110011”, “00000000 00000000” and “11111111 11111111”. The
AK4493 detects DSD mode when the input data is matched with one of
“01101001 01101001”,
“01010101 01010101” and “00110011 00110011” codes twice continuously. The AK4493 detects PCM
mode when the input data is matched with either
“00000000 00000000” or “11111111 11111111” code
twice continuously. After detecting the data mode, ADP bit is changed according to detected mode and it
is reflected to the operation on a rising edge of the LRCK/DSDR pin (#4) input data. The data mode is
kept if the input data does not match to any of the fixed codes. Input one of
“01101001 01101001”,
“01010101 01010101”, “00110011 00110011” code continuously to the DSDR pin to transition to DSD
mode from PCM mode. Input a clock toggles in N*16BICK cycles (N must be an integral number greater
than or equal to one) or a clock that keeps
“L” or “H” for 32BICK cycles to the LRCK/DSDR pin (#4). Refer
to
and
When EXDF bit =
“1”, the AK4493 detects DSD mode immediately and ADP bit becomes “1” to reflect the
detection if an input clock to the BCK/DCLK pin (#3) has rising edges more than 256 times during one
rising edge cycle of the input clock of the WCK pin (#6). The AK4493 detects EXDF mode if an input clock
to the BCK/DCLK pin (#3) has rising edge less than or equal to 256 times for two rising edge cycles of the
input clock of the WCK pin (#6) continuously. ADP bit becomes
“0” on a rising edge of the input clock to
the WCP pin (#6) when detecting EXDF mode. Input
“L” to the WCK pin (#6) to playback DSD signal
when setting EXDF bit =
“1”. Refer to
The AK4493 executes data mode detection even if there is no MCLK input when RSTN bit =
“0”.
However, the analog output becomes Hi-Z and the AK4493 enters power-off mode when MCLK is
stopped. The AK4493 resumes operation according to a data mode that is detected when MCLK is input
again. The data mode will be maintained if the input clock to the BICK/BCK/DCLK pin (#3) is stopped.
The AK4493 executes internal reset for 3~4/fs automatically when transition the data mode from DSD
mode and resumes operation.
