AsahiKASEI AK4493, Manual

Page: 90 / 104

[AK4493]
017012230-E-00 2017/12
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 DP ADP DCKS DCKB MONO DZFB SELLR SLOW
R/W R/W R R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
SLOW: Slow Roll-off Filter Enable. (
Table 25 )
0: Slow Roll-off filter disable (default)
1: Slow Roll-off filter
SELLR: The data selection of L channel and R channel to analog outputs, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
L channel output L channel data, R channel data output R channel data (default)
1: All channel output R channel data, when MONO mode.
L channel output R channel data, R channel data output L channel data
DZFB: Inverting Enable of DZF. (
Table 32 )
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
ADP: Read Back register for internal operation mode. This bit is valid when ADRE bit =
“1”.
It is invalid when ADPE bit =
“0” and readouts “0” when read.
0: PCM Mode/EXDF Mode
1: DSD Mode
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4493 should be reset by RSTN bit.