[AK4493]
017012230-E-00
2017/12
- 41 -
(2) Register Control Mode
(PSN pin = “L”)
2-
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS[2:0] bits (
). The
MCLK frequency corresponding to each sampling speed that should be provided externally (
). The AK4493 is set to Manual Setting Mode at power-up
(PDN pin = “L”→“H”). When DFS2-0
bits are changed, the AK4493 should be reset by RSTN bit.
Table 11. Sampling Speed (Manual Setting Mode in Register Control Mode)
DFS2
DFS1
DFS0
Sampling Rate (fs)
(default)
0
0
0
Normal Speed Mode
8kHz
54kHz
0
0
1
Double Speed Mode
54kHz
108kHz
0
1
0
Quad Speed Mode
120kHz
216kHz
0
1
1
Quad Speed Mode
120kHz
216kHz
1
0
0
Oct Speed Mode
384kHz
1
0
1
Hex Speed Mode
768kHz
1
1
0
Oct Speed Mode
384kHz
1
1
1
Hex Speed Mode
768kHz
Table 12. System Clock Example (Manual Setting Mode in Register Control Mode)
LRCK
MCLK (MHz)
Sampling
Speed
Fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
12.288
18.432
24.576
36.864
N/A
Oct
768kHz
12.288
24.576
36.864
49.152
N/A
N/A
Hex
(N/A: Not Available)
Table 13. System Clock Example (Manual Setting Mode in Register Control Mode)
LRCK
MCLK (MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840 24.5760
32.7680
36.8640
Normal
44.1kHz
N/A
11.2896 16.9344
22.5792 33.8688
N/A
N/A
48.0kHz
N/A
12.2880 18.4320
24.5760 36.8640
N/A
N/A
88.2kHz
N/A
22.5792 33.8688
45.1584
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760 36.8640
49.152
N/A
N/A
N/A
176.4kHz
33.8688
45.1584
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
49.152
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not Available)
