[AK4493]
017012230-E-00
2017/12
- 61 -
Table 38. DSD Signal Full-scale Detection Time Setting
DDMT1
DDMT0
Detection Time
Register Delay
0
0
256 DCLK Cycles
264 DCLK Cycles
(default)
0
1
512 DCLK Cycles
520 DCLK Cycles
1
0
1024 DCLK Cycles 1032 DCLK Cycles
1
1
128 DCLK Cycles
136 DCLK Cycles
Table 39. DSD Mode and Device Status after Full-Scale Detection (DDM bit =
“1”)
DSDD
Mode
Mute Transition time
Mute Release time
0
Normal Path
Rapidly
As ATS[1:0]
(default)
1
Volume Bypass
Rapidly
Full scale Detect flag
(DML or DMR)
DSD Data
DSD Full scale Data
DSD Data
AOUT
(DSDD bit=
“
1
”)
AOUT
(DSDD bit=
“
0
”)
RSTN bit
Internal RSTN bit
3~4/fs
DSD Full scale Data
(2)
(1)
(2)
(2)
(1)
Note:
(1) Internal reset is released after 3~4/fs by setting RSTN bit =
“0”. The internal detection flag
becomes
“1” if full-scale data is input for a period set by DDMT[1:0] bits after releasing internal
reset. In this case, excessive signals will be output from the analog output if the DSD input data is
full-scale.
(2)
Transition time of analog output data to full-scale is set by DSDF bit.
Figure 49. Analog Output Waveform with DSD Full-scale Input (DDM bit =
“0”)
