[AK4493]
017012230-E-00
2017/12
- 66 -
AOUT pin
RSTN bit
Internal RSTN bit
3
～
4/fs
PDN pin
BICK/DCLK pin
SDATA pin
ADPE bit
ADP bit
(Result of Auto DSD mode setting)
(1)
MCLK pin
DSD mode Detect
Operation Enable
LRCK/DSDR pin
PCM data
DSD data
DSD data
DSD zero
(3)
DSD zero
(6)
(2)
(2)
(4)
(4)
(5)
(5)
(7)
DSD zero
DSD zero
(8)
(9)
Hi-z
“L”
“L”
“L”
“L”
Note:
(1) Automatic mode switching between PCM/EXDF and DSD modes is enabled by setting ADPE bit =
“1”
after setting PDN pin
“L” → “H”. If RSTN bit is in default value “0”, mode detection operation will start.
(2) Mode detection is performed by monitoring input signal code pattern of the LRCK/DSDR pin. It is
executed for 34 cycles of the BICK/DCLK pin input clock and then ADP bit is changed on a rising edge
of input signal of the LRCK/DSDR pin. Mode detection is executed even when there is no MCLK
input.
(3) When DSD mode is changed, the AK4493 executes internal reset for 3~4/fs automatically.
(4) The AK4493 starts mode detection when input data of both channels are continuously zero for the
period set by ADPT[1:0] bits, and it finishes mode detection when a data that is not zero is input.
(5) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”.
In this case, delay time depends on DDMT[1:0] bits setting.
(6) In PCM mode, analog output delay time becomes 18/fs longer comparing with when setting ADPE bit
=
“0”.
(7) If DCLK input is stopped in DSD mode, the AK4493 stays in DSD mode and continues operation.
(8) Upon power up the AK4493, the AK4493 operates in PCM mode if DCLK is input and DSDR is not
input.
(9) If DCLK or DSD data input is stopped in DSD mode, the AK4493 stays in DSD mode and continues
operation. In this case, full-scale data is input to the AK4493. Excessive signal output can be avoided
by setting DDM bit =
“1” enabling automatic mute function works when detecting DSD full-scale input.
Figure 52. Changing to PCM Mode after Power-up In DSD Mode (EXDF bit =
“0”)
