artisan DAC128V, Hardware Reference Manual

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PRODUCT OVERVIEW
Copyright 2001 2-5 DAC128V HARDWARE REFERENCE
It performs no-wait ID reads, and no-wait reads from and writes to a short, eight-location
I/O map. Figure 2-4 is a physical assembly drawing for the DAC128V. Connector J1 is
located at the top of this drawing.
The DAC128V’s primary activity controller “S_DA128V” is housed within the
EPM7032LC44-10 EPLD located at U1 (just below J1 in Figure 2-4). It serves as the IP
Module transfer engine, whose responsibilities include:
•
Detection of valid I/O and ID transfer operations within their respective, fully
decoded address ranges, including the support of HOLD cycles when generated
by a carrier.
•
ID PROM emulation data pattern generation for ID read transfers.
•
DAC chip select and read/write control signal generation for I/O reads and (16-
bit only) writes where QDAC#1 at U17 is enabled for the first four I/O locations
and QDAC#2 at U18 is enabled for the last four I/O locations.
•
Direction with output-enable control signals for the data bus coupling (IPDbus
↔
DACDbus) transceivers.
The data bus transceivers are implemented using a pair of 74FCT245SC devices, and are
designated U2 and U3 (just below J1 to the right of U1 in Figure 2-4). Normally an IP
Module does not require data bus transceivers. However, since the DACs’ specified time
for release of the data bus during read operations (low impedance
→
high impedance
state change time) exceeds the maximum time allowed by the ANSI/VITA 4-1995
specification, these transceivers are employed to quickly decouple the data buses.
2.7 DAC’s Voltage Ranges
The following description provides the user with the information necessary to properly
set the voltage output ranges for the DACs on the DAC128V. In general, there are three
high-side reference voltage levels and three low-side reference voltage levels per group
of four DAC outputs. There is one combination that is not logical for normal operations,
and this is the default shipment state of the DAC128V.
CAUTION : The DAC’s produce an invalid output when both high and low
references are set to ground; the voltage outputs remain at 0.000 V (±1.0 mV)
regardless of the binary code written to their respective registers.
This “shipped-state” configuration requires the user carefully ascertain and set the output
voltage ranges prior to using the DAC128V. The intent in shipping the DAC128V in this
benign state is to attempt to minimize the potential impact on the user’s external circuitry
to which the DAC128V is attached if it is simply installed upon arrival without properly
configuring the voltage range selections. Refer to the assembly drawing in Figure 2-4 for
the following four topic areas.
2.7.1 High Reference For QDAC#1
The high-side reference for the first four DAC outputs generated by QDAC#1 at U17 is
selected by placing the jumper shunt designated as H4 onto one pair of three jumper pads
designated as J5 (ground or 0.000 V), J6 (+5.000 V), or J7 (+10.000 V). The selection is
buffered by the Operational Amplifier at U13, which provides the high-side reference
voltage for QDAC#1. Using J6 or J7 is valid for any configuration. Use of J5 should
occur if, and only if, J8 is not used for the low reference for QDAC#1 (see subsection
2.7.2, below).
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