artisan DAC128V, Hardware Reference Manual

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PERFORMANCE
Copyright 2001 4-9 DAC128V HARDWARE REFERENCE
4.7 Slew Time Tests
While the specification sheet indicates that the DAC128V outputs typically settle within
6
µ
s, and ramp at a rate of 2.2 V/
µ
s, the parameters are not always representative of those
that may be encountered in practical applications.
Figure 4-4 presents one of 66 DSO diagrams that were captured for the generation of
Table 4-6. The top trace (“D1”) is the N_ACK logic signal where the trigger was set up
for the falling edge. The bottom trace presents the DAC’s voltage output
.
NOTE : The plateau that exists where the voltage is passing through 0 V was found
to be typical for many large “step” changes, especially when heavily loaded.
Figure 4-5 Typical Slew-Time Waveform
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