artisan DAC128V, Hardware Reference Manual

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PRODUCT OVERVIEW
Copyright 2001 2-2 DAC128V HARDWARE REFERENCE
•
( )
Vout Vref
Vref Vref N
low
high low
= +
−
_
_ _
*
4096
(where N = decimal digital code)
•
Straight binary coding; DAC output at Mid-scale on power-up.
2.3 Related Products
•
Software: ‘C’ library and OS-9 device driver routines with documentation.
2.4 Block Diagram Description
IP Module
Logic Bus
Interface
& DAC
Control
Circuitry
QUAD
12-bit
DAC
Channel 0
Vref
Generator
Channel 3
QUAD
12-bit
DAC
Channel 4
Channel 7
I
P
M
O
D
U
L
E
L
O
G
I
C
B
U
S
I
P
M
O
D
U
L
E
I
/
O
Figure 2-2 DAC128V Simplified Block Diagram
Figure 2-2 presents a simplified block diagram of the DAC128V. On the left side is the IP
Module's Logic Bus connector through which all transfers between the IP Module carrier
and the DAC128V’s registers and data sources are conducted. The block labeled “IP
Module Logic Bus Interface and DAC Control Circuitry” contains the ID “PROM” data,
the DACs’ access detection and control logic, the IP Module transfer sequence/control
logic, and the data path gate control signals. All of this circuitry is implemented in one
small EPLD. The block labeled “Vref Generator” consists of a precision (+10.000)
voltage reference, a quad voltage (±10 V, ±5 V) derivation circuit with buffers, two sets
of high and low reference voltage selection blocks with buffers (one set per quad DAC),
and four reference voltage buffers with connections to the I/O connector (not shown in
this block diagram).
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