artisan DAC128V, Hardware Reference Manual

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Copyright 2001 4-1 DAC128V HARDWARE REFERENCE
4. PERFORMANCE
4.1 Overview
The purpose of this section is to provide several sets of empirical data that present typical
performance parameters beyond those provided in the specification. The important
feature is that these are typical responses for the configuration cited, and do not supplant
the maximum and minimum envelopes presented in Appendix A, SPECIFICATIONS.
Where possible, data is tabulated with only one response time (actual) performance figure
presented in order to minimize the length of the presentation.
4.2 Timing measurements
Timing measurements were conducted on the DAC128V using an HP model 16500A
Logic Analyzer with a 400 megasamples per second Digitizing Oscilloscope Module,
model 16531A, plugged into slot E, and a 1 GHz Timing Master Module, model 16515A
in slot C. The DAC128V was installed in the IP Module slot ‘A’ of a Motorola MVME-
162-01 VME processor IP Module carrier board. Figure 4-1 shows the test configuration
for the oscilloscope and state timing measurements.
1111
0000
VME Card Cage
IP Module Logic Bus
Extender Board
BHAS-IPBE1
under IP Module
IP M
odu
le
MV
ME
-16
2
To HP 1 GHz Timing Module Model
16515A and/or HP 400 MHz Digitizing
Oscilloscope Model 16531A
monitoring the IP Module Logic Bus via
Systran’s IP Module Logic Bus Extender
and Logic Bus Breakout Board
50-Position
Terminal Block
IP Module Logic Bus
Breakout Board
#BHAS-IPBB
24 IP Module Logic Bus
Extender Ribbon Cable
#BHAS-1PBEC24
3 ft 50-Position I/O
Ribbon Cable
#BHAS-RC50P03
Figure 4-1 IP Module Test Configuration for Oscilloscope and State Timing Measurements
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