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ATCA-7480 Installation and Use (6806800T17A)

Contents

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Contents

Contents

9.3.10 Payload Power Failure Cause Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

9.4 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.5 Ejector Handle De-Bounce  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
9.6 FRU Inventory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

9.6.1 MAC Address FRU OEM Records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

9.7 Reset and Power Domain  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
9.8 Power Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
9.9 BIOS Boot Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
9.10 Asynchronous Event Notification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.11 Serial Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.12 BIOS Boot Bank Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

9.12.1 Boot Bank Sensor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
9.12.2 Fail Safe Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

9.13 Glue Logic FPGA Flash Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

9.13.1 Boot Bank Sensor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
9.13.2 Fail Protect Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
9.13.3 Remote Crisis Recover Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

9.14 Settable Graceful Shutdown Timeout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
9.15 Local System Event Log (SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

A.1 Replacing the Battery  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

B

Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

B.1 Artesyn Embedded Technologies - Embedded Computing Documentation  . . . . . . . . . . . . . . . 327
B.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
B.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Summary of Contents for ATCA-7480

Page 1: ...ATCA 7480 Installation and Use P N 6806800T17A February 2015...

Page 2: ...anges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for pers...

Page 3: ...nmental and Power Requirements 43 2 2 1 Environmental Requirements 44 2 2 2 Power Requirements 47 2 3 Blade Layout 50 2 4 Switch Settings 51 2 5 Installing the Blade Accessories 53 2 5 1 DIMM Memory M...

Page 4: ...atures 85 4 4 2 Intel i350 Quad GB Ethernet Controller 86 4 4 3 Firmware Flashes 86 4 5 ATCA Fabric IF Ethernet 86 4 6 Storage Controller 87 4 7 MO297 SlimSATA Embedded Solid State Disc SSD Carrier Ri...

Page 5: ...5 FPGA Register Mapping 125 5 1 5 1 LPC I O Register Map 125 5 1 5 2 IPMC I2C Register Map 125 5 1 6 Module Identification Register 129 5 1 7 Version Register 129 5 1 8 Serial Redirection Control Reg...

Page 6: ...rnal Interrupt Status Register 152 5 1 16 6 Interrupt Mask and Map Registers 153 5 1 17 PCI Express Hot Plug I2C IO Expander Registers 155 5 1 17 1 CPU0 Hot Plug I2C IO Expander Registers 155 5 1 17 2...

Page 7: ...vice 177 6 4 3 By Boot Menu 179 6 5 IPMI Boot Parameter 180 6 6 BIOS Setup Configuration 181 6 6 1 Main 182 6 6 2 Advanced 182 6 6 3 Security 202 6 6 4 Boot 203 6 6 5 Exit 207 6 7 UEFI Secure Boot 208...

Page 8: ...2 8 3 1 Serial Output Commands 252 8 3 1 1 Set Serial Output Command 253 8 3 1 2 Get Serial Output Command 254 8 3 2 OEM Command to configure IPMI Features 255 8 3 2 1 Set Feature Configuration 256 8...

Page 9: ...pgrade 283 9 2 1 HPM 1 Components 283 9 2 1 1 IPMI Boot loader and Firmware Component 284 9 2 1 2 IAP Component 285 9 2 1 3 FPGA Component 285 9 2 1 4 BIOS Component 286 9 2 2 Retrieving Versioning In...

Page 10: ...n 314 9 11 Serial Line Selection 314 9 12 BIOS Boot Bank Selection 315 9 12 1 Boot Bank Sensor 315 9 12 2 Fail Safe Logic 316 9 13 Glue Logic FPGA Flash Selection 318 9 13 1 Boot Bank Sensor 319 9 13...

Page 11: ...nterfaces 93 Table 4 3 IPMC Debug Console Destination Selection 93 Table 4 4 SMBus Interface 95 Table 4 5 SMBus Address Map 96 Table 5 1 Register Default 99 Table 5 2 Register Access Type 99 Table 5 3...

Page 12: ...31 Line Control Register LCR 115 Table 5 32 Modem Control Register MCR 117 Table 5 33 Line Status Register LSR 119 Table 5 34 Modem Status Register MSR 122 Table 5 35 Scratch Register SCR 123 Table 5...

Page 13: ...tus Register 151 Table 5 69 Telecom Interrupt Status Register 151 Table 5 70 Telecom Interrupt Control Register 152 Table 5 71 External Interrupt Status Register 152 Table 5 72 Address Map of Interrup...

Page 14: ...Table 5 103 IPMC BIOS Communication Register 2 171 Table 5 104 IPMC BIOS Communication Register 3 171 Table 5 105 LPC Scratch Register 171 Table 5 106 IPMC Scratch Register 172 Table 6 1 Main Menu 182...

Page 15: ...mand Usage 238 Table 8 14 System Boot Options Parameter 100 Supported Parameters 239 Table 8 15 boot_order Devices 247 Table 8 16 Supported LAN Device Commands 250 Table 8 17 Supported PICMG 3 0 Comma...

Page 16: ...46 Set Payload Shutdown Time Out Command Description 275 Table 8 47 Get Module State Command Description 275 Table 8 48 Enable Module Site Command Description 277 Table 8 49 Disable Module Site Comma...

Page 17: ...nector Pinout Rows E to H 77 Figure 3 11 P23 Backplane Connector Pinout Rows A to D 77 Figure 3 12 P23 Backplane Connector Pinout Rows E to H 78 Figure 3 13 P30 Backplane Connector Pinout Rows A to D...

Page 18: ...APEI Configuration 198 Figure 6 17 IPMI Configuration 200 Figure 6 18 Security 202 Figure 6 19 Boot 203 Figure 6 20 EFI Boot Order 205 Figure 6 21 Legacy Boot Order 206 Figure 6 22 Exit menu 207 Figu...

Page 19: ...tallation requirements hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 65 describes external interfaces of the blade This includes c...

Page 20: ...ectromagnetic Compatibility EMV Elektromagnetische Vertraeglichkeit EN European Norm ESD Electrostatic Sensitive Device FPGA Field Programmable Gate Array IPMB Intelligent Platform Management Bus IPMC...

Page 21: ...hed SCSI SATA Serial ATA SCSI Small Computer System Interface SDR Sensor Data Record SMI Serial Management Interface SOL Serial over LAN SPD Serial Presence Detect SPI Serial Peripheral Interface SRAM...

Page 22: ...e screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being Ranges for example 0 4 means one...

Page 23: ...About this Manual ATCA 7480 Installation and Use 6806800T17A 23 Summary of Changes Part Number Publication Date Description 6806800T17A February 2015 Initial Version...

Page 24: ...ATCA 7480 Installation and Use 6806800T17A About this Manual 24 About this Manual...

Page 25: ...try and industrial control Only personnel trained by Artesyn Embedded Technologies or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the produc...

Page 26: ...s are considered as debug maintenance ports During normal operation no cables must be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 3m Installa...

Page 27: ...re enclosure according to the IEC EN UL CSA 60950 1 requirements All other devices that are connected only for service purposes to the VGA interface needs supervision during operation and must be disc...

Page 28: ...e EMI radiation compliancy of other configurations settings for example Spread Spectrum disabled Switch Settings Blade Malfunction Switches marked as reserved might carry production related functions...

Page 29: ...Safety Notes ATCA 7480 Installation and Use 6806800T17A 29 Environment Always dispose of used blades system components and RTMs according to your country s legislation and manufacturer s instructions...

Page 30: ...ATCA 7480 Installation and Use 6806800T17A Safety Notes 30...

Page 31: ...te an die f r Sie zust ndige Gesch ftsstelle von Artesyn Embedded Technologies Das System erf llt die f r die Industrie geforderten Sicherheitsvorschriften und darf ausschlie lich f r Anwendungen in d...

Page 32: ...kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren Die nachfolgend aufgef hrten Schnittstellen sind Wartungsschnittstellen COM ETH1 ETH2 USB1 USB2 W hrend des Normalbetriebs darf a...

Page 33: ...ngen au erhalb des Geb udes haben Ein Primary Protector wie in GR 1089 CORE beschrieben ist keine ausreichende Absicherung um die Geb ude internen Schnittstellen mit Leitungen au erhalb des Geb udes z...

Page 34: ...nn sie vom Versorgungskreislauf getrennt ist und umgekehrt Pr fen Sie deshalb immer ob die Leitung spannungsfrei ist bevor Sie Ihre Arbeit fortsetzen um Sch den oder Verletzungen zu vermeiden Die Mess...

Page 35: ...Blade installieren Batterie Besch digung des Blades Ein unsachgem er Einbau der Batterie kann gef hrliche Explosionen und Besch digungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batter...

Page 36: ...ATCA 7480 Installation and Use 6806800T17A Sicherheitshinweise 36...

Page 37: ...nnel 2 DPC resulting in a total of 16 DIMM slots 8GB and 16GB DDR4 modules in VLP available Single slot ATCA form factor 280mm x 322mm Direct CPU to PCIe interface providing 40 PCIe Gen3 lanes 8 Gbps...

Page 38: ...e MO297 type SSD module drives 1 2 Mechanical Data The following table provides details about the mechanical data of the blade Table 1 1 Mechanical Data Feature Value Height 322 25 mm 0 0 3mm Length 2...

Page 39: ...gure shows the location of the serial number label 1 4 Ordering Information The ATCA 7480 is a high performance ATCA compliant single board computer designed for demanding storage and processing appli...

Page 40: ...ore 16 DIMM sockets no memory preinstalled ATCA 7480 0GB L ATCA 7480 Blade with Dual Intel Xeon E5 2618L V3 8 Core 2 3GHz processors Haswell EP 75W TDP 2 5MB per Core Last Level Cache 256KB L2 Cache p...

Page 41: ...Introduction ATCA 7480 Installation and Use 6806800T17A 41 The following figure is a copy of Declaration of Conformity for ATCA 7480 Figure 1 2 Declaration of Conformity...

Page 42: ...Introduction ATCA 7480 Installation and Use 6806800T17A 42...

Page 43: ...the blade and dispose of it according to your country s legislation 2 2 Environmental and Power Requirements In order to meet the environmental requirements the blade has to be tested in the system i...

Page 44: ...s such as hard disks or PMC modules with more restrictive environmental requirements Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual compo...

Page 45: ...accessories Temp Change 0 25 C min according to Telcordia GR 63 CORE 0 25 C min Rel Humidity Normal Operation 5 rH to 85 rh non condensing Exceptional Operation 5 rH to 90 rh non condensing According...

Page 46: ...make sure that the temperatures at the locations specified in the Figure 2 1 are not exceeded If not stated otherwise the temperatures should be measured by placing a sensor exactly at the given locat...

Page 47: ...the accessories power requirements refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details Ta...

Page 48: ...ails of blade without any RTM Table 2 3 Power Requirements Characteristic Value Rated Voltage Exception in the US and Canada 48 VDC to 60 VDC 48 VDC Operating Voltage Exception in the US and Canada 39...

Page 49: ...simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum p...

Page 50: ...0 P32 P22 P20 P23 ZONE 1 J21 DIMM 1 J22 DIMM 2 J23 DIMM 3 J24 DIMM 4 Intel C612 PCH Wellsburg Intel i350 Powerville MO 297 Carrier 48V to 12V DCDC J15 DIMM 5 J16 DIMM 6 J17 DIMM 7 J18 DIMM 8 J14 DIMM...

Page 51: ...1 and are not covered by any other component Their location is shown in the following figure Figure 2 3 Switch Location Bottom Side of the Blade Table 2 5 Switch SW1 settings Switch Function Default...

Page 52: ...routing OFF IPMC Debug Consoleat3 pinHeader SW2 3 FPGA_PROM_SEL OFF 0 default PROM ON 1 Backup Recovery PROM OFF Use standard download PROM or redundant download PROM for FPGA configuration SW2 4 OFF...

Page 53: ...emory Modules The blade provides 16 memory slots for main memory DIMM modules of type DDR4 VLP You may install and or remove DIMM memory modules in order to match the main memory size to your needs Th...

Page 54: ...d first Table 2 8 DIMM Sockets CPU Memory channel DIMM socket Primary Secondary CPU 0 A J11 J12 B J13 J14 C J15 J16 D J17 J18 CPU 1 E J21 J22 F J23 J24 G J25 J26 H J27 J28 For optimal performance all...

Page 55: ...2 Open locks of memory module socket 3 Press module carefully into socket As soon as the memory module has been fully inserted the locks automatically close 4 If applicable repeat steps 2 to 3 to ins...

Page 56: ...urther memory modules 2 5 2 SSD Carrier and MO297 SSD Modules ATCA 7480 provides a modular solution for up to three MO297 A compliant SSDs Each SSD is connected to the Intel Wellsburg PCH via a SATA i...

Page 57: ...ector with two fingers to prevent damage to the connector 3 Fasten the SSD module to the blade using the screws supplied with the ACC kit 4 Reinstall the blade into the system as described in Installi...

Page 58: ...SD module from the blade 4 Reinstall the blade into the system as described in Installing and Removing the Blade on page 58 2 6 Installing and Removing the Blade The blade is fully compatible to the A...

Page 59: ...ed on you can disregard the blue LED and skip the respective step In this case it is purely a mechanical installation Damage of Circuits Electrostatic discharge and incorrect blade installation and re...

Page 60: ...d backplane connectors for damage or bent pins before attempting to insert a blade If any connector damage or pin damage is observed stop inserting the blade and send the damaged item to proper repair...

Page 61: ...lade into the shelf until you feel resistance Continue to push the blade gently until the blade connectors engage 5 Fully insert the blade and turn the handle towards the faceplate The latch automatic...

Page 62: ...faceplate if applicable 2 6 2 Removing the Blade This section describes how to remove the blade from an AdvancedTCA system If an RTM is connected to the front blade make sure that the handles of both...

Page 63: ...he blue LED starts blinking indicates that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently Loosen the screws of the faceplate then unlatch the handle and r...

Page 64: ...Hardware Preparation and Installation ATCA 7480 Installation and Use 6806800T17A 64...

Page 65: ...3 ATCA 7480 Installation and Use 6806800T17A 65 Controls Indicators and Connectors 3 1 Faceplate The following figure illustrates the connectors keys and LEDs available on the faceplate Figure 3 1 Fa...

Page 66: ...MC Note that this LED indicates the payload power status both in the early power state and the normal blade operation OFF Payload power is disabled Note This LED is multicolored red green yellow and i...

Page 67: ...wing connectors at its faceplate 2x Ethernet 1x Serial 2x USB 3 0 USB 2 0 H S FRU State Machine During blade installation Permanently blue On board IPMC powers up Blinking blue Blade communicates with...

Page 68: ...sed for serial line connection The pinout in the following table is used according to the Cisco like Pinout Additionally Hardware Handshake support signals are available 3 1 3 2 Ethernet Connector The...

Page 69: ...aps this interface to the serial interface COM1 The on board switch 2 1 allows to swap COM1 with COM2 making COM2 accessible through the faceplate connector instead Note that the BIOS serial redirecti...

Page 70: ...lowing figure 3 2 On board Connectors The blade provides the following on board connectors MO297 SSD module carrier connector 3 2 1 MO297 SSD Module Carrier Connector The MO297 SSD module Carrier Rise...

Page 71: ...480 Installation and Use 6806800T17A 71 The location of the MO297 SSD module carrier riser is illustrated in the following figure Figure 3 5 Location of MO297 SSD Module Connector P30 P31 P30 P32 P22...

Page 72: ...6 MO297 SSD Module Carrier Connector Pinout Table 3 3 Signal Segment Pinout Pin Number Function Description S1 GND 2nd mate S2 A Differential singal Pair A S3 A S4 GND 2nd mate S5 B Differential sign...

Page 73: ...ATCA 7480 Installation and Use 6806800T17A 73 P6 GND P7 5V Pre Charge P8 5V P9 5V P10 GND P11 RESERVED P12 GND P13 Not used 12V Pre Charge P14 Not used 12V P15 Not used 12V Table 3 4 Power Segment Pi...

Page 74: ...tors The AdvancedTCA backplane connectors reside in three zones 1 to 3 as specified by the AdvancedTCA standard and are called P10 P20 and P23 P30 P31 and P32 The pinouts of all these connectors are g...

Page 75: ...wer feed for the blade VM48_x_CON and RTN_x_CON Power enable ENABLE_x IPMB bus signals IPMB0_x_yyy Geographic address signals HAx Ground signals SHELF_GND and GND Reserved signals Zone 2 contains the...

Page 76: ...onal in the AdvancedTCA specification and are unused on the blade If the AdvancedTCA specification defines these signals as input signals they are terminated on the blade and marked as TERM_ in the fo...

Page 77: ...Controls Indicators and Connectors ATCA 7480 Installation and Use 6806800T17A 77 Figure 3 10 P20 Backplane Connector Pinout Rows E to H Figure 3 11 P23 Backplane Connector Pinout Rows A to D...

Page 78: ...the three connectors P30 P31 and P32 They are used to connect an RTM to the blade and carry the following signals Serial RS232_x_yyyy Serial ATA SATAx_yyy USB USBxy PCI Express PCIEx_yyy IPMI IPMB1_xx...

Page 79: ...7480 Installation and Use 6806800T17A 79 SAS Update channels General control signals BD_PRESENTx RTM_PRSNT_N RTM_RST_KEY RTM_RST Figure 3 13 P30 Backplane Connector Pinout Rows A to D Figure 3 14 P30...

Page 80: ...PCIE_CPU1_P3_TX_P 14 CLK100_RTM CPU1PORT3CD DP n c PCIE_CPU1_P3_TX_N 0 PCIE_CPU1_P3_TX_N 2 PCIE_CPU1_P3_TX_N 4 PCIE_CPU1_P3_TX_N 6 PCIE_CPU1_P3_TX_N 8 PCIE_CPU1_P3_TX_N 10 PCIE_CPU1_P3_TX_N 12 PCIE_CP...

Page 81: ...Controls Indicators and Connectors ATCA 7480 Installation and Use 6806800T17A 81 Figure 3 17 P32 Backplane Connector Pinout Rows A to D Figure 3 18 P32 Backplane Connector Pinout Rows E to H...

Page 82: ...Controls Indicators and Connectors ATCA 7480 Installation and Use 6806800T17A 82...

Page 83: ...tel Xeon E5 26xxL V3 Haswell EP server processors as the central processing unit CPU Each processor provides 40 PCIe lanes up to Gen3 speeds 8GT s The processors are connected with each other through...

Page 84: ...R4 2133 Very Low Profile Max 2 ranks per DIMM 8 and 16 GByte capacity Standard Voltage 1 2V Speed up to DDR4 2133 PC4 2133 for 1DPC Speed up to DDR4 1866 PC4 1866 for 2DPC Supported memory features RA...

Page 85: ...enabled in BIOS settings all PCIe devices that are connected on board or via RTM module will receive SSC clock SSC can be disabled using BIOS settings The SSC tolerance is 0 25 from nominal frequency...

Page 86: ...lash devices hosting the BIOS firmware Primary or Default BIOS Flash SPI 0 Recovery BIOS Flash SPI 1 The flash is allocated for storing the binary code of the BIOS The ATCA 7480 boots from the primary...

Page 87: ...h consists of a risercard whichprovideuptothreesocketsforSSDsandtheMO297 AcompliantSSDs Before the storage solution can be mounted on ATCA 7480 the riser card and the SSDs have to be pre mounted 4 8 H...

Page 88: ...lding block from Pigeon Point Systems PPS It is based on Microsemi Smartfusion cSOC customizable System on Chip The PPS IPMC controller is based on 32 bit Cortex M3 microcontroller operating at 50 MHz...

Page 89: ...s also called as Private I2C Bus which is connected to a FRU EEPROM temperature sensors and monitoring logic of the PIM Figure 4 2 Master Only I2C Bus Architecture SEL A2h PCA9557 38h PCA9555 4Ah PCA9...

Page 90: ...Sensor 12 Inlet Temp LM75 ATCA 7480 IPMB L1 90 IPMC Sensor 13 Outlet Temp LM75 ATCA 7480 IPMB L1 94 48V Power Interface Sensor PIM4328 ATCA 7480 IPMB L1 50 FRU EEPROM 24C512 ATCA 7480 Atmel A2F200 Ma...

Page 91: ...the IPMC serial console is also available on the faceplate serial connector It can be selected via specific IPMI OEM command 4 12 Serial Over LAN Serial over LAN SOL enables suitably designed blades a...

Page 92: ...s the following interfaces and control elements Two USB 2 0 ports Two 10 1000 1000Base T Ethernet ports Serial console port to connect to either payload or IPMC serial I F Recessed reset button Out of...

Page 93: ...is normally routed to a 3 pin on board header RS232 The IPMC Debug monitor terminal output can alsobe routed to the Faceplate The IPMC Debug Console is also available when the ATCA 7480 Payload is pow...

Page 94: ...rusted Platform Module TPM is a specific protected and encapsulated microcontroller security chip used to defend the internal data structures against real intelligent attacks The nature of this securi...

Page 95: ...own backup method uses a Super CAP with a 1 Farad capacity This provides 300 hours of RTC SRAM backup 4 20 SMBus Intel C612 PCH Wellsburg provides six SMBus interfaces Only four interfaces are used on...

Page 96: ...us Architecture Table 4 5 SMBus Address Map Device Name DeviceType Location SMBus Controller SMB Address hex SPD EEPROM NA DDR4 module CPU 0 memory controller AB A0 SPD EEPROM NA DDR4 module CPU 0 mem...

Page 97: ...H A0 SPD EEPROM NA DDR4 module CPU 0 memory controller GH A8 IPMC Sensor 12 Inlet Temp LM75 ATCA 7480 Intel Wellsburg PCH 90 IPMC Sensor 13 Outlet Temp LM75 ATCA 7480 Intel Wellsburg PCH 94 48V Power...

Page 98: ...Functional Description ATCA 7480 Installation and Use 6806800T17A 98...

Page 99: ...ternal logic level Table 5 2 Register Access Type Access Description r Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 h...

Page 100: ...and the address range REGISTERS and within the address ranges of COM1 or COM2 only when enabled during Super IO configuration are decoded by the LPC core 5 1 1 1 2 LPC Memory Decoding The LPC interfac...

Page 101: ...ress 0x80 The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED Displays The IPMC can read the POST code using the SPI interface wit...

Page 102: ...figuration State When the Super IO is not in the Configuration State reads return 0xFF and write data is ignored 5 1 3 1 Entering the Configuration State The device enters the Configuration State by t...

Page 103: ...ster locations Reads to reserved registers may return non zero values Writes to reserved locations may cause system failure 5 1 3 4 1 Global Control Configuration Registers The Super IO Global Registe...

Page 104: ...erial Port 1 0x05 Logical Device 5 UART2 Serial Port 2 A write to this register selects the current logical device This allows access to the control and configuration registers for each logical device...

Page 105: ...0 LPC r Table 5 13 Global Super IO SERIRQ and Pre divide Control Register Index Address 0x29 Bit Description Default Access 0 SERIRQ enable 0 disabled Serial interrupts disabled 1 enabled Logical dev...

Page 106: ...ed to select a specific logical device register These registersarethenaccessedthroughtheDATAPORT TheLogicalDeviceregistersareaccessible only when the device is in the Configuration state The logical r...

Page 107: ...16 Logical Device Base IO Address MSB Register Index Address 0x60 Bit Description Default Access 7 0 Logical Device Base IO Address MSB 0 LPC r w Table 5 17 Logical Device Base IO Address LSB Register...

Page 108: ...0x7 IRQ7 0x8 IRQ8 0x9 IRQ9 0xA IRQ10 0xB IRQ11 0xC IRQ12 0xD IRQ13 0xE IRQ14 0xF IRQ15 0 LPC r w 7 4 Reserved 0 LPC r An Interrupt is activated by enabling this device offset 0x30 setting this registe...

Page 109: ...Latch Bit DLAB which is the MOST significant bit of the Serial Line ControlRegister SCR affectstheselectionofcertainoftheUARTregisters TheDLABbitmust be set high by the system software to access the B...

Page 110: ...value of the data byte at the top of the FIFO Table 5 23 UART Register Overview LPC IO Address DLAB Bit value Description Base 0 Receiver Buffer RBR Read Only Base 0 Transmitter Holding THR Write Only...

Page 111: ...a value in the Interrupt Identification Register Each of the four interrupt types can be disabledbyresettingtheappropriatebitoftheIERregister Similarly bysettingtheappropriate bits selected interrupts...

Page 112: ...Register IER if DLAB 0 continued LPC IO Address Base 1 Bit Description Default Access Table 5 27 UART Interrupt Priorities2 Priority Level Interrupt Source 1 highest Receiver Line Status One or more...

Page 113: ...able 5 29 Interrupt Identification Register Decode Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control 0b0001 None No Interrupt is pending 0b0110 1 Receiver Line Status Ov...

Page 114: ...e interrupt or writing to the Transmitter FIFO 0b0000 4 Modem Status Clear to Send Data Set Ready Ring Indicator Received Line Signal Detect Reading the modem status register Table 5 29 Interrupt Iden...

Page 115: ...e Control Register The read capability simplifies system programming and eliminates the need for separate storage in system memory 5 4 Reserved 0 LPC w 7 6 Receiver FIFO interrupt trigger level 00 1 b...

Page 116: ...ecked as cleared When bits 3 and 5 are set and bit 4 is cleared the parity bit is transmitted and checked as set If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disa...

Page 117: ...tput in high state 0 LPC r w 2 User output control signal OUT1 1 OUT1 output in high state 0 OUT1 output in low state Not supported 0 LPC r w 3 User output control signal OUT2 1 OUT2 output in high st...

Page 118: ...st been received In FIFO mode these three bits of status are stored with each received character in the FIFO LSR shows the status bits of the character at the top of the FIFO When the character at the...

Page 119: ...data received 0 No new data 0 LPC r 1 Overrun error OE indicator When OE is set it indicates that before the character in the RBR was read it was overwritten by the next character transferred into the...

Page 120: ...d every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its as...

Page 121: ...T indicator TEMT bit is set when the THR and the TSR are both empty When either the THR or the TSR contains a data character TEMT is cleared In the FIFO mode TEMT is set when the transmitter FIFO and...

Page 122: ...When DDSR is set and the modem status interrupt is enabled a modem status interrupt is generated 1 Change in state of DSR input since last read 0 No change in state of DSR input since last read 0 LPC...

Page 123: ...ing either of the divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load Access to the divisor latch can be done with a word write 6 Complement of the ri...

Page 124: ...6X Divisor For example if the pre divider is 26 the UART_CLK is 1 8461538MHz When the divisor is 12 the baud rate is 9600 A divisor value of 0 in the Divisor Latch Register is not allowed Table 5 36 D...

Page 125: ...ap Some FPGA registers may be accessed via IPMC Private I2C transactions Slave address 0x7F See Table 5 38 FPGA Register Map Overview An IPMC write access to an address not listed in this table or mar...

Page 126: ...0x12 r w1c r BIOS IPMC Watchdog Timeout Register See Table 5 53 0x13 w BIOS Push Button Enable Register See Table 5 54 0x14 r w1c r OS Reset Source Register See Table 5 55 0x15 r w1c r OS IPMC Watchd...

Page 127: ...ee Table 5 77 0x41 r w r PCH Output Enable Register See Table 5 78 0x42 r w RTM SPI Address Command Register See Table 5 79 0x43 r w RTM SPI Write Register Table 5 80 RTM SPI Read Register See Table 5...

Page 128: ...See Table 5 96 0x6A 0x6B r w Telecom Clock Monitor Upper Limit Register See Table 5 97 0x74 r w r BIOS Version Register 1 See Table 5 98 0x75 r w r BIOS Version Register 2 See Table 5 99 0x76 r w r B...

Page 129: ...ase 5 1 8 Serial Redirection Control Register BIOS sets the corresponding bit which is used for serial redirection The IPMC uses this information to route the corresponding port to serial IPMC interfa...

Page 130: ...0 LPC r w IPMC r 1 COM2 use for serial redirection 0 COM2 not used for serial redirection 1 COM2 used for serial redirection 0 LPC r w IPMC r 7 2 Reserved 0 r When both control bits are enabled bit 1...

Page 131: ...plate Note Setting may be overwritten by IPMC Software controlling Bit 4 Ext SW2 1 0 OFF 1 ON r 1 Inverted level of signal IPMC_SER_2_HEADER which is controlled by switch SW2 2 0 IPMC Serial Debug Int...

Page 132: ...s up signal SLP_A_ becomes high The table below shows all possible failing states and their coding Table 5 44 ME Power Failure State Register Address Offset 0x08 Bit Description Default Access 2 0 ME...

Page 133: ...power good lost 5 ME_WAIT_OFF ASW power good lost Other These values will never occur Table 5 46 ME Power Failure Cause Register Address Offset 0x09 Bit Description Default Access 0 Active Sleep Well...

Page 134: ...ling causes are latched Table 5 47 Payload Power Failure State Register Address Offset 0x0A Bit Description Default Access 4 0 Payload Power Failure State Latched last Payload Power state when failure...

Page 135: ...tages have failed which have been already enabled and sampled good 0xA VDDQ_ENABL E Timeout debugdisabled after280ms VDDvoltagesarenot good Other cause One or more voltages have failed which have been...

Page 136: ...issue Board wakes up within 5s timeout 1 Wakeup failure Board does not wake up SLP_S3_ stays low within 5s timeout PWR_GOOD 0 IPMC r 1 VCCIO power good failure signal PWRGD_PVCCIO 0 No VCCIO power iss...

Page 137: ...0 75V power issue 1 0 75V power failure PWR_GOOD 0 IPMC r 5 3 3V and 1 05V power good failure signal PWRGD_V3P3_V1P05 0 No 3 3V and 1 05 power issue 1 3 3V and 1 05 power failure PWR_GOOD 0 IPMC r 6...

Page 138: ...PP CPU0 power failure PWR_GOOD 0 IPMC r 1 VPP CPU1 power good failure signal PWRGD_PVPP_EFGH 0 No VPP CPU1 power issue 1 VPP CPU1 power failure PWR_GOOD 0 IPMC r 2 VDD CPU0 power good failure signal P...

Page 139: ...signal PWRGD_PVCCIN_CPU1 0 No VCCIN CPU1 power issue 1 VCCIN CPU1 power failure PWR_GOOD 0 IPMC r Table 5 51 Payload Power Failure Cause Register 3 continued Address Offset 0x0D Bit Description Defaul...

Page 140: ...two reset sources go active at the same time OS should never write to this register Table 5 53 BIOS Reset Source Register Address Offset 0x10 Bit Description Default Access 0 PWR_GOOD Payload Power on...

Page 141: ...ates that the associated reset source is masked 5 1 12 3 BIOS IPMC Watchdog Timeout Register When one of the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is set the corresponding BIOS I...

Page 142: ...PMC Watchdog Timeout Register Address Offset 0x12 Bit Description Default Access 0 BIOS IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 1 BIOS IPMC Pre Timeout 1 IPM...

Page 143: ...s go active at the same time 5 1 12 6 OS IPMC Watchdog Timeout Register BIOS should never write to this register Table 5 57 OS Reset Source Register Address Offset 0x14 Bit Description Default Access...

Page 144: ...watchdog timeout event When the IPMC Watchdog Timeout bit is set from low to high the corresponding bits in Table 5 55 and Table 5 58 are set BIOS should never write to this register Table 5 58 OS IPM...

Page 145: ...ces go active at the same time Table 5 59 IPMC Watchdog Timeout Register Address Offset 0x16 Bit Description Default Access 0 IPMC Watchdog Timeout 0 No IPMC Watchdog Timeout 1 IPMC Watchdog Timeout o...

Page 146: ..._GOOD 0 IPMC r w1c 7 IPMC_RST_ REQ_ Payload Reset from IPMC 1 Reset occurred PWR_GOOD 0 IPMC r w1c Table 5 60 IPMC Reset Source Register continued Address Offset 0x17 Bit Description Default Access IP...

Page 147: ..._ADR_IRQ_ signal is asserted When PCH signals completion with assertion of ADR_COMPLETE the Reset State Machine asserts PCH_SYS_RST_ If ADR is not enabled PCH_SYS_RST_ is generated immediately without...

Page 148: ...5 63 DIMM ADR Status Register Address Offset 0x1A Bit Description Default Access 0 IndicatesiftheADRfeatureisenabled GPIO37of Cavecreek 0 ADR disabled PCH_ADR_IRQ_ is driven high 1 ADR enabled PCH_ADR...

Page 149: ...can initiate a NMI Host can identify NMI comes from IPMC Table 5 65 S States Control Register Address Offset 0x1F Bit Description Default Access 0 SCI pulse generation Minimum low pulse width is 45ms...

Page 150: ...l and Status Registers The interrupt status registers indicate events of the interrupt input signals When an interrupt event occurred the corresponding status bit is read 1 Writing 1 of the correspond...

Page 151: ...how how to clear the corresponding interrupt status bits Table 5 68 Internal Interrupt Status Register Address Offset 0x21 Bit Description Default Access 0 IPMC signals interrupt Host clears flag 0 LP...

Page 152: ...ion Default Access 3 0 Telecom CLK_MONITOR_FINISHED interrupt enable Enable Disable interrupt for the corresponding Clock source 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r w 7 4 Telecom CL...

Page 153: ...caseallinterruptsourcesneed to be of type level active low Each interrupt source has an Interrupt Mask and Map Register See Table 5 72 7 1 Reserved 0 r Table 5 71 External Interrupt Status Register Ad...

Page 154: ...r 2 IRQ1 0x03 Frame number 3 IRQ2 SMI_ 0x04 Frame number 4 IRQ3 0x05 Frame number 5 IRQ4 0x06 Frame number 6 IRQ5 0x07 Frame number 7 IRQ6 0x08 Frame number 8 IRQ7 0x09 Frame number 9 IRQ8 0x0A Frame...

Page 155: ...e Hot Plug Virtual Pin Port Register Table 5 74 Table 5 74 Hot Plug Virtual Pin Port Register Address Offset CPU0 Port 1 0x30 Port 2 0x31 Port 3 0x32 Port 4 0x33 CPU1 Port 1 0x38 Port 2 0x39 Port 3 0x...

Page 156: ...to mechanically hold the card in place and can be open closed manually Electromechanical latch is used to electro mechanically hold the card in place and is operated by software MRL is used for card e...

Page 157: ...ction status bit CURRENT_BOOT_SELECT and the IPMC selected Boot Flash status bit TARGET_BOOT_SELECT Table 5 75 Address Control for PCA9555 Internal Register Address Offset CPU0 Device1 Slave address 0...

Page 158: ...ENT_BOOT_SELECT Current Boot Flash selection Is valid until next platform reset 0 r 3 1 Reserved 0 r 4 TSOP or PLCC Boot select Signal BOOT_TSOP 0 TSOP selected 1 PLCC selected Ext 0 SW1 3 OFF 1 SW1 3...

Page 159: ...als RTM_SPI_SCK RTM_SPI_SS_ RTM_SPI_MISO and RTM_SPI_MOSI are used to support a SPI master protocol The signal RTM_SPI_MISO is also used to signal an ARTM interrupt to the base board See Chapter 5 18...

Page 160: ...the SPI device A write access to the RTM SPI Address Command Register with the Command Bit 1 Read starts a SPI read transaction This contains the data read from the SPI device Table 5 79 RTM SPI Addre...

Page 161: ...w IPMC r 2 Control output Signal UC2_EQ_RX 0 UC2_EQ_RX is driven low 1 UC2_EQ_RX is tri state 0 LPC r w IPMC r 3 Control output Signal UC2_EQ_TX 0 UC2_EQ_TX is driven low 1 UC2_EQ_TX is tri state 0 LP...

Page 162: ...us Register Address Offset 0x4B Bit Description Default Access 0 RTM power good status 0 RTM power not stable or RTM not powered 1 RTM power good Ext RTM_PWRGD IPCM r 7 1 Reserved 0 IPCM r Table 5 85...

Page 163: ...ED_RED_ is driven high LED off 1 LED_RED_ is driven low LED on 0 r w 2 Control user LED output Signal LED_USER1_ 0 LED_USER1_ is driven high LED off 1 LED_USER1 is driven low LED on 0 r w 3 Control us...

Page 164: ...ot present Socket is empty Ext r 3 CPU1 Presence Detection Status of signal CPU1_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 7 4 Reserved 0 r Table 5 89 CPU Error Status Re...

Page 165: ...ee table below Table 5 90 Supervised Telecom Clocks Reference List Number Name Description 0 SYSCLK_IN_CLK1A CLK1A from backplane 1 SYSCLK_IN_CLK1B CLK1B from backplane 2 SYSCLK_IN_CLK2A CLK2A from ba...

Page 166: ...ed Telecom Clock 0 to 3 Corresponding bit is set when measurement has finished Clearing bit triggers new measurement 0 LPC r w1c 7 4 Reserved 0 r Table 5 93 Telecom Clock Monitor Out of Range Register...

Page 167: ...refer to the clock selected with Table 5 94 Table 5 94 Telecom Clock Monitor Select Register Address 0x63 Bit Description Default Access 1 0 Select supervised Telecom Clocks See Table 5 90 Supervised...

Page 168: ...open for 4096ms 15 Gate is open for 8192ms 16 Gate is open for 16384ms 17 and all others Gate is open for 32768ms 0 LPC r w Select Time base for clock supervision with Period Mode 0 Period Counter in...

Page 169: ...mer base 65535 Overflow Clock to fast for time base Period Mode 0 No clock edge sampled Clock to fast for time base 1 65534 Number of clocks during one supervised clock period 65535 Overflow Supervise...

Page 170: ...93Telecom Clock Monitor Out of Range Register 0xFFFF LPC r w Table 5 99 BIOS Version Register 1 Address Offset 0x74 Bit Description Default Access 7 0 BIOS Version bits 0 to 7 0 LPC r w IPMC r Table 5...

Page 171: ...D 0 LPC r w IPMC r w Table 5 103 IPMC BIOS Communication Register 2 Address Offset 0x7B Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 5 104 IPMC BIO...

Page 172: ...Maps and Registers ATCA 7480 Installation and Use 6806800T17A 172 Table 5 106 IPMC Scratch Register Address Offset 0x7E Bit Description Default Access 7 0 LPC Scratch bits PWR_GOOD 0 IPMC r w LPC r...

Page 173: ...234 The BIOS used on the blade is based on the Insyde UEFI BIOS with several Artesyn Embedded Technologies extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI...

Page 174: ...a normal PC keyboard input The serial console redirection feature can be configured via a setup utility 6 2 1 Requirements for Serial Console Redirection For serial console redirection the following...

Page 175: ...ta bits No parity 1 stop bit 6 2 3 Connecting to the Blade Procedure In order to connect to the blade using the serial console redirect feature proceed as follows 1 Configure terminal to communicate u...

Page 176: ...t the bottom of the menu Additionally an item specific help is displayed on the right side of the window Figure 6 1 Main menu Make sure that BIOS is properly configured prior to installing the operati...

Page 177: ...ppy CD ROM and hard disk Solid State Disk connected to the SATA interface available only when SSD SATA is assembled Storage devices connected to the SAS controller by RTM Network Front Panel Ethernet...

Page 178: ...ows 1 From the menu select Boot 2 Select the order of the devices from which BIOS attempts to boot the operating system If BIOS is not successful at booting from one device it tries to boot from the n...

Page 179: ...9 6 4 3 By Boot Menu 1 Press F4 key to enter the Boot Menu 2 Override existing boot sequence by selecting another boot device from the boot list Figure 6 2 Boot Menu If the selected device does not lo...

Page 180: ...s are loaded when selecting the Restore Defaults Item on BIOS Save and Exit Menu A detailed description of the IPMI Boot Parameter and the corresponding IPMI commands is available in System Boot Optio...

Page 181: ...or Save and Exit option 3 BIOS writes the parameter to the BIOS Parameter in the Flash 4 BIOS writes the parameter to the IPMI Boot Parameter USER area Load Defaults 1 User enters BIOS setup and selec...

Page 182: ...enu options 6 6 2 Advanced Platform Information Figure 6 4 Main Menu Table 6 1 Main Menu Item Values IPMI Boot parameter Description System Time 15 48 21 Set the Time Use Enter to switch between Time...

Page 183: ...BIOS ATCA 7480 Installation and Use 6806800T17A 183 This shows important information about Platform CPU QPI and Memory Figure 6 5 Platform Information...

Page 184: ...onfiguration Table 6 2 Advanced RTM Configuration Item Values IPMI Boot parameter Description Auto Detect RTM Enabled Disabled rtm_auto Ifenabled theRTMisdetectedandtheRTMPCI Express parameter are set...

Page 185: ...Zone 3 connector RTM CPU0 PCIe Port 3D Auto Gen1 2 5GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu0_3d Selects CPU0 PCIe Port 3D Speed for Zone 3 connector RTM CPU1 PCIe to RTM Width X4x4x4x4 x4x4x8 x8x4x4 x8...

Page 186: ...GT s rtm_cpu1_3c Selects CPU1 PCIe Port 3C Speed for Zone 3 connector RTM CPU1 PCIe Port 3D Auto Gen1 2 5GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu1_3d Selects CPU1 PCIe Port 3D Speed for Zone 3 connecto...

Page 187: ...les Disables Front Panel Ethernet PCIe SR IOV Support Enabled Disabled pci_sriov Enables Disables PCI Express Single Root I O Virtualization PCIe ARI Enabled Disabled pci_ari Enables Disables Alternat...

Page 188: ...ues IPMI Boot parameter Description Intel VT for Directed I O VT d Enabled Disabled vtd Enables Disables Intel Virtualization Technology for Directed I O VT d by reporting the I O device assignment to...

Page 189: ...ription SATA Controller Enabled Disabled sata Enables Disables SATA Device Operation Mode IDE AHCI RAID sata_mode Selects the controllers Operation Mode Aggressive LPM Support Enabled Disabled sata_al...

Page 190: ...e storage support under UEFI and DOS environment If UEFI Only is set it supports only in UEFI environment USB1 Front Panel Enabled Disabled usb1 Enables Disables USB Front Panel Port 1 USB2 Front Pane...

Page 191: ...nfiguration Table 6 7 Advanced Processor Configuration Item Values IPMI Boot parameter Description Socket 0 Core Disable 0 to 3FFE cpu0_dism Core Disable Bitmap Hex Value 0 Enable all cores Valid Rang...

Page 192: ...improve the virtualization performance and robustness Hardware Prefetcher Enabled Disabled cpu_hp Enables Disables the hardware prefetcher Adjacent Cache Prefetch Enabled Disabled cpu_acp When enable...

Page 193: ...Values IPMI Boot parameter Description Enhanced Intel SpeedStep Enabled Disabled cpu_ss Enables Disables Enhanced Intel SpeedStep Technology P States Turbo Mode Enabled Disabled cpu_tm Enables Disable...

Page 194: ...States will have lower wake up latencies CPU C3 report Enabled Disabled cpu_c3 Enables Disables CPU C3 ACPI C3 report to OS CPU C6 report Enabled Disabled cpu_c6 Enables Disables CPU C6 ACPI C3 report...

Page 195: ...Advanced Memory Configuration Item Values IPMI Boot parameter Description Memory Frequency Auto 1333 1600 1867 2133 mem_speed Maximum Memory Frequency Selections in MHz Halt on Training Error Enabled...

Page 196: ...RAS Configuration Item Values IPMI Boot parameter Description RAS Mode Disable Mirror Lockstep Mode mem_ras Enables Disables RAS modes Enabling Sparing and Mirroring is not supported Incase if enable...

Page 197: ...ion Table 6 11 Advanced Console Redirection Item Values IPMI Boot parameter Description TerminalType VT_100 VT_100 VT_UTF8 PC_ANSI con_tt Sets Console Redirection terminal type Baud Rate 115200 57600...

Page 198: ...direction stop bits Flow Control None RTS CTS XON XOFF con_fc Sets Console Redirection flow control type C R After Post Yes No con_ap Continue Console Redirection after POST when OS is loaded Table 6...

Page 199: ...Platform Error Interface APEI and Windows Hardware Error Architecture WHEA AEPI extends hardware error reporting mechanisms and brings them together as components of a coherent hardware error infrastr...

Page 200: ...PMI Boot parameter Description IPMI KCS Interrupt Enabled Disabled ipmi_irq Enables Disables usage of Host Interface KCS interrupt KCS interrupt is hardwired to IRQ 6 OS Watchdog Timer Enabled Disable...

Page 201: ...No Change failsafe Enables Disables Fail Safe Policy Enabled IPMC will switch the BIOS boot bank if the FRB2 watchdog expires No Change Fail Safe Policy will not be changed by BIOS Show Sensor Data Sh...

Page 202: ...rity configuration Figure 6 18 Security Table 6 15 Security Item Values IPMI Boot parameter Description TPM Operation No Operation Disable and Deactivate Enable and Activate tpm_operation Enables Disa...

Page 203: ...Boot configuration Figure 6 19 Boot Table 6 16 Boot Item Values IPMI Boot parameter Description Boot Type Dual Boot Type Legacy Boot Type UEFI boot Type boot_type SelectboottypetoDualtype Legacytypeor...

Page 204: ...t is required Fabric Network Boot Enabled Disabled boot_fabricnet Controls execution of the Option ROM for all Fabric Network Ethernet controller Select Enabled when Fabric Network Boot is required RT...

Page 205: ...to configure the order of the EFI Boot devices Use the Up and Down keys to select a device Use and keys to move the devices up or down With the key a boot device can be enabled or disabled If the boo...

Page 206: ...configure the order of the Legacy Boot devices Use the Up and Down keys to select a device Use and keys to move the devices up or down With the key a boot device can be enabled or disabled If the boot...

Page 207: ...Exit menu Figure 6 22 Exit menu Table 6 17 Exit Item Values IPMI Boot parameter Description Exit Saving Changes Saves the changes made and then exits the system Save Change Without Exit Saves the cha...

Page 208: ...ry Settings setup item This activatesUEFI Secure Boot 5 Press F10 key to save the changes 6 8 Restoring BIOS Default Settings Thebladeprovides anon boardconfigurationswitch that allows to load BIOS se...

Page 209: ...ID Shows SEL and Sensor Values in BIOS setup BIOS creates the DMI structure type 38 to provide IPMI host interface information to the OS BIOS reads and creates the IPMI boot parameters which are store...

Page 210: ...t the flooding of the event logs The parameters are Error Threshold Correctable memory errors are logged when the threshold is reached The first correctable memory error is always logged Error Logging...

Page 211: ...and Use 6806800T17A 211 PCI PERR PCI Parity Error Sensor Critical Interrupt Offset 04h PCI PERR PCI SERR PCI System Error Sensor Critical Interrupt Offset 05h PCI SERR Table 6 18 Logged Error Events c...

Page 212: ...ilt In Self Test BIST Error 30h Exception Divide Error 31h Exception Invalid Opcode 32h Exception Stack Fault 33h Exception GP Fault 34h Exception Math Error 35h Exception Alignment Check 36h Exceptio...

Page 213: ...Cache initialization 0Ch Console input initialization 13h Starting Operating System FDh OEM Error Extension Supported Event Data3 FDh OEM Error Extension 90h Reboot after a FRB2 Watchdog Timeout 91h...

Page 214: ...de the BIOS Update tool for Linux is provided with Basic Blade Services BBS The BIOS can also be upgraded via IPMI HPM 1 Hardware Platform Management IPM Controller Firmware Upgrade Refer to Firmware...

Page 215: ...M test 08h Tune CPU frequency ratio to maximum level 09h Setup BIOS ROM cache 0Ah Enter Boot Firmware Volume 70h Super I O initial 71h CPU Early Initial 72h Multi processor Early initial 73h HyperTran...

Page 216: ...h Enter DXE core 8Ch iFFS Transition Start 8Dh iFFS Transition End 40h TPM initial in DXE 41h South bridge SPI initial 42h Setup Reset service DXE_CF9Reset 43h South bridge Serial GPIO initial DXE_SB_...

Page 217: ...57h SMI test 58h VTD Initial 59h Legacy BIOS initial 5Ah Legacy interrupt function initial 5Bh ACPI Table Initial 5Ch Setup SB SMM Dispatcher service DXE_SB_Dispatch 5Dh Setup SB IOTRAP Service 5Eh B...

Page 218: ...E controller initial 1Fh SATA controller initial 20h SIO controller initial 21h ISA BUS driver initial 22h Floppy device initial 23h Serial device initial 24h IDE device initial 25h AHCI device initia...

Page 219: ..._DEVICE FBh UEFI Boot Start Image PostBDS_START_IMAGE FDh Legacy 16 boot entry FEh Try to Boot with INT 19 A0h Identify Flash device in SMM A2h SMM service initial A6h OS call ACPI enable function A7h...

Page 220: ...from S3 E4h System wakeup from S4 E5h System wakeup from S5 A0h QPI Initialization Initialize QPI inuput structure default values A1h QPI Initialization Collect info such as SBSP Boot Mode Reset type...

Page 221: ...ion DIMM Detect B1h Memory Initialization Clock B2h Memory Initialization Read SPD data B3h Memory Initialization Early Init B4h Memory Initialization Rank Detection B5h Memory Initialization Early Ch...

Page 222: ...BIOS ATCA 7480 Installation and Use 6806800T17A 222...

Page 223: ...ilable on the base interface The sideband interface of the Intel Forthville is used to transmit receive its terminal characters via base interface You can configure the SOL parameters via standard IPM...

Page 224: ...can configure the following SOL parameters You can use standard IPMI commands or the ipmitool to modify the parameters 7 3 1 Using Standard IPMI Commands This example shows how to setup the SOL confi...

Page 225: ...In Progress Commit ipmicmd k f 0 c 1 1 0 2 smi 0 7 3 2 Using ipmitool The example below shows how to setup a LAN configuration parameter for a potential SOL session with ipmitool for base 0 channel 5...

Page 226: ...fault Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available root localhost ipmitool lan print 2 Set in Progress Set Complete Auth Type Support Auth Type Enable C...

Page 227: ...efer to Installing the ipmitool on page 223 3 Apply an IP address to the ATCA 7480 SOL interface For details see to Configuring SOL Parameters on page 224 4 Change user and password if necessary Defau...

Page 228: ...fer to the ipmitool documentation available on http ipmitool sourceforge net To see the BIOS serial interface in SOL Session operational Use For help it might be necessary to write a logical 1 into FP...

Page 229: ...system interface Table 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Comments Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Re...

Page 230: ...er Access 0x06 0x07 0x43 Get User Access 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Paylo...

Page 231: ...Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B 0x43 Add SEL Entry 0x0A 0x0B 0x44 Clear SEL 0x0A 0x0B 0x47 Get SEL Time 0x0A 0x0B 0x48 Set SEL Time 0x0A 0x...

Page 232: ...0x05 0x24 Get Sensor Hysteresis 0x04 0x05 0x25 Set Sensor Threshold 0x04 0x05 0x26 Most of the threshold based sensors have fixed thresholds Before using this command check whether threshold setting...

Page 233: ...different purposes When using the Get Set System Boot Options commands except for parameter 100 use the response request data fields with the Set Selector and the Block Selector set to 0x00 When using...

Page 234: ...ts 7 2 Reserved Bit 1 FPGA configuration stream load 0 Load configuration stream from default boot flash 1 Load configuration stream from backup boot flash Note The new FPGA configuration stream is lo...

Page 235: ...interprets the parameters and executes the boot process accordingly The storage area is divided into two parts the default area and the user area The user area can be read and written by an IPMI user...

Page 236: ...t of the boot options to be used when setting or reading the System Boot Options parameter 100 On some blades with particular firmware types changing a boot parameter in the firmware setup menu change...

Page 237: ...separated by a zero byte The end of the boot parameter data is indicated by two zero bytes Allowed and supported name value pairs are blade specific Details are given below n 1 n 2 16 byte checksum ov...

Page 238: ...maining bytes in the addressed storage area block are left unchanged Response Data 1 0x00 Write successful 0x80 Boot parameter storage not supported by the IPMC 0x81 Storage area is locked by another...

Page 239: ...he maximum size of writable storage area your software can perform a series of read accesses while incrementing the block selector with each access Once the error code C9 is returned the limit has bee...

Page 240: ...onnector RTM auto gen1 gen2 gen3 rtm_cpu0_3d Selects CPU0 PCIe Port 3D Speed for Zone 3 connector RTM auto gen1 gen2 gen3 rtm_cpu1_bif Selects CPU1 PCIe Bifurcation for Zone 3 connector RTM X4x4x4x4 x...

Page 241: ...I O Virtualization on off pci_ari Alternative Routing ID nterpretation ARI on off pci_64bit 64 bit BAR support for PCI devices on off clock_ssc Spread Spectrum Clock on off Vtd Intel Virtualization T...

Page 242: ...Enable all cores Valid Range 0 to 3FFE 3FFF Disabling all cores Invalid Hex Value 0 to 3FFE cpu1_dism Core Disable Bitmap Hex Value 0 Enable all cores Valid Range 0 to 3FFE 3FFF Disabling all cores I...

Page 243: ...n off cpu_ppw Turbo Mode Performance Watt tradi optim cpu_cstates CPU C State support on off cpu_cslimit Package C State limit c0c1 c2 c6nr c6r no cpu_c3 CPU C3 report on off cpu_c6 CPU C6 report on o...

Page 244: ...es off mirror lockstep mem_sparing Memory Rank Sparing on off mem_ps Memory Patrol Scrub on off mem_ds Memory Demand Scrub on off con_tt Serial console terminal type vt100 vt100 utf8 ansi con_br Seria...

Page 245: ...n off apei_uefiver UEFI revision of APEI error format uefi22 uefi23 ipmi_irq IPMI KCS Interrupt on off osboot_wd OS Watchdog Timer on off osboot_wd_tout 0S Watchdog Timeout in minutes 1 2 3 5 7 10 15...

Page 246: ...ot PXE Boot capability ipv4 ipv6 ipv4v6 legacy boot_frontnet Front Panel Net Boot on off boot_basenet Base Network Boot on off boot_fabricnet Fabric Network Boot on off boot_rtmnet RTM Network Boot on...

Page 247: ...ontnet1 Front Panel Network 1 frontnet2 Front Panel Network 2 basenet1 Base Network 1 basenet2 Base Network 2 fabricnet11 Fabric Network 1_1 fabricnet12 Fabric Network 1_2 fabricnet21 Fabric Network 2...

Page 248: ...ifabricnet11 EFI Fabric Network 1_1 IPv4 efiffabricnet12 EFI Fabric Network 1_2 IPv4 efifabricnet21 EFI Fabric Network 2_1 IPv4 efifabricnet22 EFI Fabric Network 2_2 IPv4 efirtmnet1 EFI RTM Network 1...

Page 249: ...twork 3 IPv6 efirtmnet4v6 EFI RTM Network 4 IPv6 efirtmnet5v6 EFI RTM Network 5 IPv6 efirtmnet6v6 EFI RTM Network 6 IPv6 efirtmnet7v6 EFI RTM Network 7 IPv6 efirtmnet8v6 EFI RTM Network 8 IPv6 efirtmn...

Page 250: ...0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Parameters 0x0C 0x0D 0x21 Get SOL Configuration Parameters 0x0C 0x0D 0x22 Table 8 17 Supported PICMG 3 0 Commands C...

Page 251: ...Info 0x2C 0x2D 0x18 Set AMC Port State 0x2C 0x2D 0x19 Get AMC Port State 0x2C 0x2D 0x1A Get FRU Control Capabilities 0x2C 0x2D 0x1E Get target upgrade capabilities 0x2C 0x2D 0x2E Get component proper...

Page 252: ...th PICMG HPM 1 specific commands Before sending any of these commands the shelf management software must check whetherthereceivingIPMIcontrollersupportsArtesynEmbeddedTechnologiesspecific IPMI command...

Page 253: ...d 1 LSB of Artesyn IANA Enterprise number A value of 0xCD has to be used 2 Second byte of Artesyn Embedded Technologies IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn Embedded...

Page 254: ...dded Technologies IANA Enterprise number Table 8 20 Response Data of Set Serial Output Command continued Byte Data Field Currently only BIOS output is supported Table 8 21 Request Data of Get Serial O...

Page 255: ...a Field Table 8 22 Response Data of Get Serial Output Command Byte Data Field 1 Completion code 2 LSB of Artesyn Embedded Technologies IANA Enterprise number 3 Second byte of Artesyn Embedded Technolo...

Page 256: ...see Table 8 25 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h FFh Debounce timer timeout value in 100ms 6 Persist...

Page 257: ...iption 3 03h Handle Debounce 224 E0h FAILSAFE Function Enable Disable For details see Fail Safe Logic on page 316 225 E1h FAIL PROTECT Function Enable Disable For details see Fail Protect Logic on pag...

Page 258: ...SB of Artesyn IANA Enterprise Number A value of 00h shall be used 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h F...

Page 259: ...71 0x2E 0x2F 0x0B Disable Payload Control Table 8 41 on page 271 0x2E 0x2F 0x0C Reset IPMC Table 8 42 on page 272 0x2E 0x2F 0x0D Hang IPMC Table 8 43 on page 272 0x2E 0x2F 0x0E Graceful Reset Table 8...

Page 260: ...bugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate...

Page 261: ...threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 8 28 2 Manual Standalone for a description refer to Table 8 28 Bit 0 Contr...

Page 262: ...0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 Rese...

Page 263: ...rise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00...

Page 264: ...rise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given...

Page 265: ...le If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages th...

Page 266: ...et to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to go...

Page 267: ...a 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394...

Page 268: ...first byte 2 0A byte 3 40 byte 4 00 Table 8 35 Set Hardware Address Command Description continued Type Byte Data Field Table 8 36 Get Handle Switch Command Description Type Byte Data Field Request Dat...

Page 269: ...4 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from har...

Page 270: ...Communication Time Out Command Description continued Type Byte Data Field Table 8 39 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enter...

Page 271: ...a 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394...

Page 272: ...Byte first byte 1 0A byte 2 40 byte 3 00 4 Reset Type Code 0x00 Cold IPMC reset to the Current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for a descripti...

Page 273: ...upon receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to not...

Page 274: ...er the payload Interface to notify the IPMC that the payload shutdown is complete To avoid deadlocks that may occur if the payload software does not respond the IPMC provides a special time out for th...

Page 275: ...nterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 5 Time Out measured in hundreds of milliseconds LSB first Response Data 1 Completion Code 2 4 PPS IANA P...

Page 276: ...is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload...

Page 277: ...quest Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Ent...

Page 278: ...the carrier SDR repository Table 8 50 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte...

Page 279: ...nds and provides hardware interfaces for other system management features such as Hot Swap control LED control power control as well as temperature and voltage monitoring The IPMC also supports a Keyb...

Page 280: ...mands directed to the MMC will be bridged by the IPMC The Intel CPU communicates with the IPMC using the KCS interface of the IPMC The FRU inventory System Event Log SEL events and the SDR information...

Page 281: ...block diagram of ATCA 7480 I2 C IPMB 0 IPMB A IPMB B IPMB L I2 C b u f f e r b u f f e r LPC Microsemi A2F200M3F_CS288 IPMC PCH ME 0x96 0x98 Intel CPU Intel NIC SOL ATMEGA 128 MMC at RTM NCSI Lattice...

Page 282: ...s responsible for providing a means for measuring time and detecting timeout conditions The device drivers are responsible for implementing high level interfaces to the hardware Network Stack The netw...

Page 283: ...MB 0 IPMB L Interface Communication x Standalone Mode Application Layer x IRQ Handlers x Low Level Initialization x I O Device Drivers Active IPMI firmware x FRU HotSwap Management IPMC x Sensor Manag...

Page 284: ...eNVM depending onthebootflagsindicatingsuccessfulboot ThebootloaderisalsousedasHPM 1component however there is no backup image Table 9 1 HPM 1 components ID Payload cold reset required Deferred activa...

Page 285: ...MR A2F AMCc IPMI building block from Pigeon Point is implemented within an FPGA logic block from Microsemi Inc Its fabric can be upgraded via HPM 1 firmware upgrade This process is referred to In Appl...

Page 286: ...ity to switch the banks without upgrading an HPM 1 firmware at all For details see System Boot Options Commands on page 233 Automatic rollback is implemented via failsafe architecture For details see...

Page 287: ...ision BANK A Operational Firmware Name IPMI F W Firmware Version 2 0 00000002 BANK B Rollback Firmware Name IPMI F W Firmware Version 2 0 00000002 BANK D Operational Firmware Name IPMI B L Firmware Ve...

Page 288: ...supports upgrades with the ipmitool Artesyn recommends to use the Pigeon Point System modified Ipmitool 1 8 13 pps2 or later versions 9 2 3 1 Installing ipmitool In case of ipmitool 1 8 13 pps2 is alr...

Page 289: ...even if the payload is not powered on M4 The BASE Ethernet controller is powered with management power 9 2 3 3 1 KCS The standard way to upgrade the firmware of the payload is through the KCS interfac...

Page 290: ...e interface and from payload host Thus firmware upgrades can be executed much faster This is especially useful with BIOS firmware upgrades when 16 Mbytes of data need to be transferred via IPMI Make s...

Page 291: ...rmcp P rmcp H 172 16 0 221 k gkey hpm upgrade root bios hpm activate PICMG HPM 1 Upgrade Agent 1 0 9 Validating firmware image integrity OK Performing preparation stage Services may be affected durin...

Page 292: ...ds assertion and de assertion information and a brief description of the sensor purpose Table 9 2 ATCA 7480 Specific Sensors Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1...

Page 293: ...Physical IPMB 0 0xF1 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 7 4 Channel Number 3 0 Reserved reading 0x0 IPMB A disabled IPMB B disabled 0x1 IPMB A enabled IPMB B disabled 0x2 IPMB A disabled I...

Page 294: ...l Asrt Auto 4 Mid air temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 5 3 3V MGMT Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 6 12V Voltage 0...

Page 295: ...discrete 0x6F 0x0 0x1 0x2 0x3 0x8 See IPMI Spec 0xFF 0x0 Timer expired 0x1 Hard Reset 0x2 Power Down 0x3 Power Cycle 0x8 Timer Interrupt Asrt Auto 13 Fw Progress System Firmware Progress 0x0F Sensor...

Page 296: ...completed 0x6 bootcompleted Asrt Auto 15 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0xFF 0xFF 0x0 No Bootable media 0x1 Non bootable diskette 0x2 PXE Server not foun...

Page 297: ...x7 0xFF 0xFF 0x0 Correctable ECC 0x1 Uncorrectable ECC 0x4 Memory Device Disabled 0x5 Correctable ECC 0x6 Presence detected 0x7 Configuration error Asrt Auto 18 Critical IRQ Critical Interrupt 0x13 Se...

Page 298: ...Power Supply Failure detected Asrt Auto 23 48v A Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 24 48v B Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc...

Page 299: ...r Supply Failure detected Asrt Deass Auto 30 48V B Supply Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass...

Page 300: ...x5 0xFF 0xFF 0x0 S0 0x3 S3 0x5 S5 Asrt Auto 34 CPU Status Processor 0x07 Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 IERR 0x1 Thermal Trip Asrt Auto 35 ME Pwr Fail OEM 0xE0 Sensor specific dis...

Page 301: ...40 CPU0 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 41 CPU1 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 42 DDR1 J11 temp Temp 0x01 Thresh...

Page 302: ...uc unc Asrt Deass Auto 52 DDR11 J23 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 53 DDR12 J24 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 5...

Page 303: ...ADT7461 L2 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 62 ADT7461 R2 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 63 IPMC POST Management...

Page 304: ...ion about how the boot up sequence is initiated by hard reset by soft reset and so on The Memory sensor implemented with sensor type 0x0C Memory is used to inform the IPMC about defect DIMMs detected...

Page 305: ...h and reports an event in the case where the Digital Power Monitor disables power on by its own As a result of this the IPMC will pro actively transition the IPMC from M4 to M6 to M1 with a cause code...

Page 306: ...ate 0 Primary side Alarm is not set 1 Primary side Alarm is set Bit 1 Voltage Feed B Enabled 0 Enable B is Disabled 1 Enable B is Enabled Bit 0 Voltage Feed A Enabled 0 Enable A is Disabled 1 Enable A...

Page 307: ...their coding see Table 5 45 9 3 9 Payload Power Failure State Sensor The IPMC evaluates the Payload Power Failure Register to report power failures at the payload domain When a Payload Power failure...

Page 308: ...r Failure Cause Register 2 covers the main board voltages For more information see Table 5 50 The Payload Power Failure Cause Register 3 covers CPU specific voltages When a CPU is not mounted detected...

Page 309: ...d accidental FRU extraction caused by service teams during servicing other FRUs The ejector handle de bounce function can be enabled disabled and configured with the use of the OEM command Set Get Fea...

Page 310: ...d of List Version 7 End of List Set to 1b for the last record 6 4 Reserved Write as 000b 3 0 Record format version Write as 2h 2 1 Record Length 3 1 Record Checksum zero checksum 4 1 Header Checksum z...

Page 311: ...ecifies a pool of MAC addresses with M count 3 6 MAC Address Canonical form the LSB least significant bit first Table 9 9 Interface Type Assignments Interface Type Description 01h ATCA Base Interface...

Page 312: ...e Product Version Item Value Description Dynamic power reconfiguration support No While the blade is powered itsupportsonly one power level Dynamic power configuration No The power level is fixed and...

Page 313: ...he system manager may decide from which boot device the blade should boot from The boot configuration parameters are stored as sets of parameter name and value pairs Theycanbeeasilyenhancedandthereare...

Page 314: ...tions before the payload is gracefully rebooted shut down Graceful Reboot and Graceful Shutdown is also communicated to the Intel CPU via internal communication channel 9 11 Serial Line Selection TheA...

Page 315: ...ctive and standby is done by the IPMC The BIOS Boot Bank Selection is implemented such that swapping the SPI flashes is not in effect immediately To ensure that the active BIOS bank cannot be overwrit...

Page 316: ...ion and parameter 224 For details see Set Feature Configuration on page 256 BIOS setup menu Typically failsafe is used to protect a BIOS firmware upgrade to recover even when the boot image programmed...

Page 317: ...over from scenarios Missing or defect boot block Firmware image has a bad checksum Figure 9 3 FailSafe Failsafe enabled Swap Boot Bank and send a System Firmware Hang event to the ShMM Watchdog expire...

Page 318: ...Logic FPGA Flash Selection The ATCA 7480 provides redundant FPGA flashes for both manual and automatic crisis recoveries The general concept is that there is always an active and a standby SPI flash d...

Page 319: ...on Sensor on page 304 9 13 2 Fail Protect Logic FailProtectisamechanism implementingautomaticFPGAbankcrisisrecovery Itobservesthe FPGAbootphase toswaptheFPGAbanksandtoreloadtheFPGA incaseoftheFPGAfirm...

Page 320: ...red Failed once start Deassert signal FPGA_PROGRAM Evaluate signal FPGA Done Yes Yes Yes Both FPGA banks corrupted Crisis Recovery FPGA Load Done Swap Boot Bank to protect working image Remote Crisis...

Page 321: ...ent Reading Type Code 0x6F Sensor Specific Event Data Byte 1 0xA1 System Firmware Hang Event Data Byte 2 0x00 CPU instance Event Data Byte 3 0xXX Failed Boot Bank ID 0 Bank A 1 Bank B Payload software...

Page 322: ...EL entry in the buffer All events are automatically logged locally to the local SEL before being passed to the Shelf s SEL which includes all events that occur from the local MMC To support the local...

Page 323: ...1 Replacing the Battery Some blade variants contain an on board battery Its location is shown in the following figure A battery less variant based on SUPERCAP is available on demand Figure A 1 Locatio...

Page 324: ...ata Loss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Therefore replace the battery before seven years of actual battery use have elaps...

Page 325: ...ce the battery 1 Remove battery 2 Install the new battery following the positive and negative signs PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the bat...

Page 326: ...Replacing the Battery ATCA 7480 Installation and Use 6806800T17A 326...

Page 327: ...e For released products you can also visit our Web site for the latest copies of our product documentation 1 Go to www artesyn com computing support product technical documentation php 2 Under FILTER...

Page 328: ...rmation is subject to change without notice Table B 2 Manufacturer s Documents Company Document Title Intel 6300ESB I O Controller Data sheet 82546EB GB Gigabit Ethernet Controller Documentation 6700P...

Page 329: ......

Page 330: ...syn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2015...

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