Main Board
USA MAV500/MKVI Service Manual
10.4.18
FPGA JTAG Interface (Not fitted)........................................... 10-22
10.4.19 Mechanical
Switches.............................................................. 10-22
10.4.20 Backplane
Board .................................................................... 10-23
10.5
Removal and Replacement Procedures ............................. 10-23
10.6 Description
of
Connectors .................................................. 10-24
10.6.1 Fan
Connector - J1................................................................. 10-25
10.6.2 Communications
Configuration Board - J3 ............................. 10-25
10.6.3
PCI Mezzanine Connectors - J5 and J6 ................................. 10-27
10.6.4 Smart
Card - J7 ...................................................................... 10-28
10.6.5
Memory Expansion Board - J9 and J12 ................................. 10-29
10.6.6 Optically
Isolated
Connector - P20 ......................................... 10-32
10.6.7 Miscellaneous
Connector - P22.............................................. 10-34
10.6.8
Security and I/O Expansion Connector - P21 ......................... 10-36
List of Figures
Figure 10-1 Logic Cage and Location of Main Board ................................................... 10-4
Figure 10-2 System Architecture .................................................................................. 10-5
Figure 10-3 Main Board Block Diagram........................................................................ 10-7
Figure 10-4 Main Board Layout ..................................................................................... 10-8
Figure 10-5 Hitachi SH-4 Microprocessor Block Diagram ........................................... 10-11
List of Tables
Table 10-1 Optical Security - Typical Assignment ...................................................... 10-17
Table 10-2 Mechanical Security - Typical Assignment ............................................... 10-17
Table 10-3 Hopper Control Signals............................................................................. 10-18
Table 10-4 Coin Handling Signals .............................................................................. 10-19
Table 10-5 SPI Channel Signals................................................................................. 10-19
Table 10-6 Power Control System Signal Lines ......................................................... 10-21
Table 10-7 Description of Connectors ........................................................................10-24
Table 10-8 Fan Connector - J1 ...................................................................................10-25
Table 10-9 Communications Configuration Board Connector - J3 ............................. 10-25
Table 10-10 PCI Mezzanine Connector - J5...............................................................10-27
Table 10-11 PCI Mezzanine Connector - J6...............................................................10-28
Table 10-12 Smart Card Connector - J7..................................................................... 10-28
Table 10-13 Memory Expansion Board Connector - J9.............................................. 10-29
Table 10-14 Memory Expansion Board - J12 ............................................................. 10-30
Table 10-15 Optically Isolated Connector - P20 ......................................................... 10-32
Table 10-16 Miscellaneous Connector - P22.............................................................. 10-34
Table 10-17 Security and I/O Expansion Connector - P21......................................... 10-36
10-2
28-00486-00
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© Copyright (ATI) Aristocrat Technologies, Inc. 2002
