USA MAV500/MKVI Service Manual
Main Board
The data is usually replicated three times, so that each chip contains identical data.
Each memory is checked against the other to verify the stored data is correct.
Write access is mutually exclusive with only one chip writeable at a time. If an error
occurs and memory is overwritten, only one of the three devices can be corrupted.
On reset, the bank-select register selects bank 0, which does not exist. The SRAMs
are located at banks 1,2, and 3.
The three SRAM chips are powered from two separate batteries, further reducing the
possibility of losing data.
EEPROMs
The system implements two serial EEPROMs. The minimum requirement is
128 bytes per EEPROM.
Memory Expansion Port
The memory expansion port is primarily designed to add EPROM and/or PCMCIA to
the Main Board. The Memory Expansion Board enables 64 Mbytes and more of
EPROM to be directly addressed together with signals to accommodate paged
memory, external DRAM emulation and debug facilities. The on-board EPROM is
disabled when the appropriate signal is asserted from the Memory Expansion Board.
The Memory Expansion Board interfaces with the Main Board via a 96-way
DIN41612 connector (J12) and a 4
−
way half-DIN41612 connector (J9).
10.4.8
Battery Backup Circuit
The Main Board has two lithium batteries for SRAM, the Real Time Clock and
security. One battery is used for SRAM, RTC, and security, and the other is allocated
to two SRAMs. Each battery is mounted in a socket with a security tie wrap.
CAUTION
Danger of explosion if battery is incorrectly
replaced. Dispose of used batteries according
to manufacturer’s instructions.
A resistor and diode combination in series prevents reverse charging of the battery.
A lithium battery can potentially explode if reverse charged.
The Main Board includes circuitry to test each battery under CPU control. The test
places a resistor load on the battery and checks the voltage after a short delay (55.6
ms). The load is enabled from a monostable so that a fault in the software will not
discharge the battery.
The battery end life is at 2.0
V DC, below which the memory and logic are no longer
guaranteed to work. The test will indicate a battery failure at 2.5 V DC.
28-00486-00
10-15
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved.
© Copyright (ATI) Aristocrat Technologies, Inc. 2002.
