USA MAV500/MKVI Service Manual
Main Board
10.4 Technical Description
The Technical Description begins with two diagrams: a block diagram introducing
the various functional subsystems of the Main Board and a layout diagram indicating
the location of components on the Main Board. A description of the various
functions and components of the Main Board follow these diagrams.
SDRAM
SDRAM
(16-Mbyte)
(32-Mbyte)
SH-4
CPU
PLX9054
PCI Bridge
FPGA
PCI
Mezzanine
Connector
PowerVR
Graphics
PCI Bus
Local Bus
A(25:0)
AD(63:0)
FA(4:0)
AD
(2
5:
5)
Address
Buffers
Address
Buffers
Data
Buffers
MPX
SH-4: Hitachi SuperH SH-4 Series RISC Microprocessor
FPGA: Field Programmable Gate Array
SRAM: Static Ramdom Access Memory
PCI: Peripheral Component Interconnection
EPROM: Erasable Programmable Read Only Memory
UART: Universal Asynchronous Receiver Transmitter
MPX
DATA(7:0)
DATA(63:0)
ADDR(25:0)
ADDR(25:0)
MVP
Peripheral
Interface
SRAM
UART
MVP
Backplane
Interface
PC
C
a
rd
AD
D
R
ES
S (
2
5:
0
)
16
32
64
Memory
Expansion
Board
Interface
Game
EPROM
System
EPROM
I0150
Figure 10-3 Main Board Block Diagram
28-00486-00
10-7
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved.
© Copyright (ATI) Aristocrat Technologies, Inc. 2002.
