ADSP-21065L SHARC User’s Manual 1-13
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The Program Sequencer includes a 32-word instruction cache that enables
three-bus operation for fetching an instruction and two data values. The
cache is selective—only instructions whose fetches conflict with program
memory data accesses are cached. This enables full-speed execution of core
looped operations, such as digital filter, multiply-accumulates and FFT
butterfly processing.
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The DSP core has four buses:
• Program Memory Address
Transfers the addresses for instructions.
• Data Memory Address
Transfers the addresses for data.
• Program Memory Data
Transfers instructions.
Since the PM Data bus is 48-bits wide, it can accommodate the
48-bit instruction width. Fixed-point and single-precision float-
ing-point data is aligned to the upper 32 bits of this bus.
• Data Memory Data
Transfers data.
The DM Data bus is 40-bits wide and provides a path to transfer the
contents of any register in the processor to any other register or to
any data memory location in a single cycle. Fixed-point and sin-
gle-precision floating-point data is aligned to the upper 32 bits of
this bus.
