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1-6 ADSP-21065L SHARC User’s Manual
40-Bit Extended Precision
. The ADSP-21065L handles 32-bit IEEE
floating-point format, 32-bit integer and fractional formats (twos-comple-
ment and unsigned), and extended-precision, 40-bit IEEE floating-point
format. The processor carries extended precision throughout its computa-
tion units, limiting intermediate data truncation errors. When working
with data on-chip, the processor can transfer the extended-precision,
32-bit mantissa to and from all computation units. The fixed-point for-
mats have an 80-bit accumulator for true 32-bit fixed-point computations.
Dual Address Generators
. The ADSP-21065L has two data address gener-
ators (DAGs) that provide immediate or indirect (pre- and postmodify)
addressing. It supports modulus and bit-reverse operations with no con-
straints on data buffer placement.
Efficient Program Sequencing
. In addition to zero-overhead loops, the
ADSP-21065L supports single-cycle setup and exit for loops. Loops are
both nestable (six levels in hardware) and interruptible. The processors
support both delayed and non-delayed branches.
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The ADSP-21065L includes several enhancements that simplify system
development. The enhancements occur in three key areas:
• Architectural features supporting high-level languages and operat-
ing systems.
• IEEE 1149.1 JTAG serial scan path and on-chip emulation features.
• Support of IEEE floating-point formats.
